ATA-4 / UDMA-33 IDE IP Core
Features | Command Set | System Architecture
Download: Altera Target 
| Xilnx Target
Description
The ATA-4 / UDMA-33 IDE Core is a drop-in ATA-Host IP core used for interfacing to an ATA-device. It handles all transactions on the IDE bus for various commands that are dispatched from the system. After a command is dispatched, the ATA-core executes the command on the ATA device. Once the command execution is completed, the final status is reported to the system side. At that time, the system can execute a new command.
Features
- ATA/ATAPI-4 standard compliant host
- UDMA-33 transfer speed capabilities (33 MB/s max transfer speed)
- RX and TX FIFOs for data transfer through the Core
- DMA/UDMA and PIO data transfers supported
- Dedicated signal for polling ATA-device status
- Dedicated signal for executing Software Reset command
- Two Clock domains: Core Clock and System Clock domains
- Dedicated system side input bus for writing data to the ATA device
- Dedicated system side output bus for data read from the ATA device
- Required Core Clock Speed: 100MHz
- Available PIO Modes: 0 and 4
- Number of ATA devices supported on the IDE Bus: 1
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