Nuvation Pioneers Design in High-Speed Search Engine Interface

San Jose, Calif., June 1, 2000 — Nuvation Labs Corporation has announced the successful design of a High Speed Search Engine Interface for Mountain View based Netlogic Microsystems (www.netlogicmicro.com).

The Search Engine Interface is a half-million gate FPGA design implemented in Virtex-E, the most advanced family of Xilinx chips. The design is highly modular and flexible and allows direct interfacing to multiple popular Network Processors and all of Netlogic’s Network Co-processors and Content Addressable Memories.

Nuvation performed all aspects of the FPGA design, from extracting requirements, project management, architecture design and documentation, Verilog coding, functional simulation, synthesis, place and route, static timing analysis and post-layout timing analysis. The half-million gate design was successfully completed from requirements to bit-stream in less than six (6) weeks!

According to FPGA Design Engineer David Tang, "This highly efficient and modular interface allows faster time-to-market for system designers as it dramatically lighten the load of firmware development for controlling logic to the search engines."

About Nuvation

Nuvation is a leading Electronics Design Services (EDS) firm that provides ASIC, FPGA, board, and firmware design services for the embedded systems industry. Nuvation's design experience spans industries such as Communications, Consumer Electronics, Medical, and Security/Defense. Founded in 1997 and based in San Jose, California, Nuvation's customers include a number of notable companies such as Altera, Lucent, HP, JDS Uniphase, Infineon, LeapFrog, SanDisk, Finisar, and Trimble Navigation. Nuvation is a wholly-owned subsidiary of IAR Systems (OMX:IAR). More information is available at www.nuvation.com

# # #

Contacts:

Chris Hallahan
VP Sales & Marketing
Nuvation
408-228-5580 x122
chris.hallahan@nuvation.com