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Fall 2004 Frontpage | Subscribe | Feedback 


In This Issue

IP Cores: Speeding to Market

The New CycloneBot: Spinning Titanium

Designing High-Speed Traces (P.2)

Device Spotlight:
TI DM642 DSP

Hike For A Cure: Challenge 2004

Message from Nuvation's CEO


Previous Issues

ATCA: The NexGen Telecom Standard

Video Processing in FPGA vs. DSP

Designing High-Speed Traces (P.1)

H.264: The New Video Standard

Ethernet over Sonet Solutions

Minimize Noise in your Circuits

PCI Express Lane

CycloneBot Design Revealed

The Signal Integrity FAQ

Device Spotlight: ADI TigerSharc

Device Spotlight: Motorola HCS08

Device Spotlight: Altera's Nios II



Nuvation HEADLINES 

New IP

»  ATA 4/5, UDMA 33/66 Core for Xilinx Spartan 3
»  ATA 4/5, UDMA 33/66 for Altera Cyclone
»  GFP-F IP Core
»  PCI-Express Core

New Affiliations

»  W&W Communications H.264 CODEC Integration Partner
»  Lattice Certified FPGA Design Center
»  Intel PCI Express Developers Network
»  ADI Certified DSP Partner

Device Spotlight:
DM642 DSP from TI

The Texas Instruments TMS320DM642 (or "DM642") Digital Signal processor is this issue's Device Spotlight. The DM642 device is based on the second-generation high-performance, advanced VelociTIT very-long-instruction-word (VLIW) architecture (VelociTI.2T) developed by TI. It is fully software compatible with TI's popular C64x DSP family, and includes some whiz-bang features, which optimize it for digital media applications. This chip provides an awesome platform for running your most advanced algorithms involving video and audio capture, compression, decompression, filtering, scaling, network streaming, motion detection, object tracking, and dozens of other applications.
There are so many cool features to talk about with this chip, so it is hard to know where to start. At its core is an instruction machine with 64 general-purpose, 32-bit registers, as well as two 32-bit multipliers, and six independent ALUs - with VelociTI.2T extensions. The VelociTI.2T extensions are new instructions which accelerate the performance in video and imaging applications and extend the parallelism within the chip. Because of this highly parallel architecture, the DM642 (running at 720MHz) can execute four 16-bit multiply-accumulates (MACs) per cycle for a total of 2.4 billion MACs per second (GMACS), or eight 8-bit MACs per cycle for a total of 5.76 GMACS. Perfect for all your 2D FFTs, filters, transforms and compression algorithms, which have to run on real-time video streams.

Video processing applications tend to be large memory-hogs. As such, the DM642 supports a glueless interface to many different types of memory, including SRAMs, EEPROMs, SDRAM, SBSRAM, ZBT SRAM, and others. The memory interface is 64-bits wide, allowing rapid data transfers between the DSP and memory. Internally, the DM642 sports a two-level cache: 128Kbit each for Level 1 program and data, and 2Mbit space mapped for Level 2. Externally, the DSP is able to address up to 1 GByte of total external memory.

Perhaps the best aspect of this device is the on-board peripherals. This chip can talk to almost everything! The peripheral set includes:

  • Three configurable digital video ports: Supports video capture or display. Glueless interfaces to common video protocols such as: CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M.
  • One 10/100 Mb/s Ethernet MAC with MDIO module: Only requires an external PHY to implement Ethernet connectivity.
  • One PCI bus interface (shared with Ethernet MAC pins): Interfaces to 33/66 MHz PCIv2.2 standard.
  • One Multi-channel buffered audio serial port (McASP): Communicates with audio input/output devices such as codecs. Supports I2S, S/PDIF, IEC60958-1, AED-3, CP-430 formats.
  • Two Multi-channel buffered serial ports (McBSPs): Supports common serial protocols such as SPI
  • VCXO Interpolated control port DAC: 1-bit integrating DAC used for MPEG audio-video synchronization
  • I²C controller
  • Three 32-bit timer modules
  • Sixteen GPIO with interrupt capability
  • Flexible PLL clock generator
Whether you plan to capture or display, the video ports and serial-audio ports make it a snap to transport all-digital media within any design. Furthermore, the flexible collection of interfaces such as I²C and GPIOs makes it easy to add sensors and control, and the PCI and Ethernet interfaces make this device an ideal centerpiece for PC expansion cards, or embedded Internet appliances.

Nuvation chose the DM642 as the processing engine for one of its embedded design projects in the Fall of 2004. In our design, the DM642 captured digital video from a front end imaging chipset, and ran a special compression algorithm known as H.264 to reduce the size of the data, before streaming it out of the Ethernet MAC. H.264 (also known as AVC) is a brand-new video standard, which provides significantly more compression than the older, MPEG-4 layer 2 format. However, H.264 is very compute-intensive, our research found that the DM642 was the only single DSP capable of performing real-time H.264 compression at reasonable levels of power dissipation and cost. In fact, at present, the DM642 is the DSP of choice for companies who are inventing the newest compression and image processing techniques today.

The DM642 requires a 3.3V I/O and a 1.4V core supply, and is available in 500, 600, and 720MHz speed grades.
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