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| Fall 2004 | Frontpage | Subscribe | Feedback | ||
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Nuvation FPGA/ASIC IP Cores Get your license to speed time-to-market   IP Cores are becoming extremely popular with our customers, greatly accelerating product development cycles and reducing NRE with plug & play solutions. Nuvation developed its first FPGA IP Core in 2002, the GEOS-10, to multiplex Gigabit Ethernet (GbE) streams to/from SONET. We built this major IP core on the theory that legacy telecom networks would need to support datacom GbE traffic. Our first customer showed up a month after our GEOS product announcement. One of the largest semiconductor companies in the world needed a bridge chip between their 10 channel GbE MAC/PHY and their OC-192 SONET Framer chip. A demonstration platform was built and the solution showcased at N+I and other trade shows -- streaming multiple channels of broadcast video over 40 kilometers of optical fiber.
Nuvation's GEOS has now been integrated with major telecom equipment company line cards, successfully passed demanding carrier trials, and is deployed worldwide at the core of MAN and WAN equipment. We thought it was a good start. We're also grateful for the customers and business partners that took that initial step with us, confident that we could mux/de-mux, frame/de-frame, and pass data at these speeds with 0 dropped packets and no off-chip memory. Nuvation has since gone on to develop many additional cores and is aggressively developing new IP for release in 2005. Following is a synopsis of our IP availability for first-half 2005. If we can help accelerate your product development with any of these cores, or if you need something not currently available on the market, please let us know. Telecom/Datacom IP GEOS Family (Gigabit Ethernet Over SONET) Nuvation's GEOS cores mux GbE data to/from SONET. We have OC-192 (10Gbps) and OC-48 (2.488Gbps) variants. GEOS cores are designed to interface between the GbE MAC/PHY and SONET Framer chips. The GEOS cores are packed with features such as GFP framing/de-framing, traffic statistics per port, CPU interface, configurable destination addresses, and jumbo packet handling up to 100% bandwidth of 9.6K packets. Our new GEOS 2+2 (OC-48) fits in a sub-$50 FPGA, carrying more bandwidth and at a lower price than competing ASSP solutions. GEOS-8 and GEOS-10 (OC-192) continue to attract new licensees. GFP-F/T The GEOS cores include General Framing Procedure (GFP) IP. We have some customers that require GFP but not the full functionality of GEOS (i.e. 10GbE XAUI to SONET). Frame-mapped GFP is used in GEOS (GFP-F) and is licensable today as a standalone core. Transparent-mode GFP (GFP-T) is used in storage networking environments (typically FibreChannel) and is soon to be released. DOS Family (Data Over SONET) As FPGAs continue to increase in density and resources, we have advanced GEOS to include the MAC functionality. Both Ethernet or FibreChannel (FC) MACs are supported, the MACs are available from MoreThanIP. We can integrate various combinations of 10/100/1000 Ethernet MACs and 1/2G FC MACs with our GEOS engine and GFP-F and GFP-T cores. Other IP can be integrated as well for specialized applications such as broadcast video. The combinations are endless, which is a great advantage over rigid ASSP solutions. Interface Cores ATA-4/5 ATA-4 and ATA-5 cores were introduced in early 2004 and have been hardware validated with our test platforms and with licensee products. ATA-4 and 5 are parallel interface implementations commonly used to connect hard disk drives (HDDs). RAID servers, defense-related embedded systems, professional video systems, and other systems that use low-cost FPGAs can benefit from Nuvation ATA cores. We frequently see our IP integrated with PCI and/or embedded processors. SATA-I/II HDDs are going to serial interfaces. SATA-I is becoming more pervasive, with a 1.5Gbps serial interface. SATA-II is emerging, with a 3Gbps interface. Nuvation's SATA cores can be licensed now with final release in late Q1. PCI-Express Nuvation's PCI-Express (PCIe) cores are targeted for 8 and 16 lane implementations. Nuvation has already developed the PCIe physical layer, up to 16 lanes (32 channels), and has hardware validated this core with a lead customer in an automated test equipment application. Due to the nature of the target system, data & link layers were not required for our lead customer's implementation. We are currently developing these layers for general release of x1/2/4/8/16 implementations. Nuvation is not aware of any other developers that have accomplished x8 and x16 designs, and x8 is required for true 10G throughput. If you are looking for a PCIe for interfacing SPI-4.2, XAUI, or other protocols and would like to be considered for our early-release program, please let us know. Video IP Nuvation's IP design team includes many engineers with extensive video processing backgrounds. We are planning to introduce IP cores for broadcast and consumer video markets throughout 2005. Our first release targeted for Picture-in-Picture with FPGA and DSP co-processing architectures. If you are a developer of broadcast or consumer video products and have IP requirements that are not currently being served, please contact us and we can discuss our mutual roadmaps under NDA. Customer service · To subscribe yourself or a friend, please click here. · Questions? Comments? Send us your feedback. |
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