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Designing High-Speed Traces (Part 2)
Signal Integrity Problems & Solutions
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  Designing high-speed traces involves many design principles that need to be taken into consideration to maintain signal integrity. In a 3-part article series, we will explore some of the main guidelines, and discuss methods to achieve the best possible signal quality for your project. In Part 1 (Summer 2004 issue of CURRENT), we discussed the treatment of high-speed traces as lossy transmission lines. In Part 2, we will explore impedance matching and critical spacing between traces.
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Impedance Matching
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Signals that propagate down the line will have different delays and losses as a function of the various frequency components of the signal. Since most "signals" in a digital application are pulses the signals require a very broad bandwidth.
For example, a 1ns wide with a rise and fall time of 50ps pulse has a spectral width of 20GHz. If the transmission line is properly designed and it is impedance matched at the source and the load and the dielectric material of the PWB has a flat dielectric constant over the required bandwidth than all the component frequencies of the pulse will travel down the line at the same velocity. The increasing resistance of the line will attenuate the higher frequency components of the pulse more than the lower frequency components resulting in an increase in the effective rise time of the pulse at the load. If the line is not matched, it has an effective capacitance or inductance causing reflections to occur. Reflections and various frequency components go back and forth up and down the line and depending on the electrical length of the line will cause overshoot, undershoot and suck out. Proper termination of the transmission lines is required to reduce unwanted distortion and timing errors.
There are basically two ways to terminate the lines parallel or series, series termination must be placed as close to the driver as possible while the parallel termination must be placed as close to the receiver as possible. An unterminated section of line is defined as a stub and can appear as an inductor, capacitor, parallel tuned circuit or series tuned circuit depending on its electrical length.
Series termination works by absorbing reflections from the load into the termination and preventing the reflections from "bouncing" off the driver and reappearing at the load. Parallel termination provides the same effect by absorbing the signal at the load end and thus preventing reflections off the mismatched load. The magnitude of reflections can be determined by calculating the reflection coefficient using the following expression:
Reflection coefficient, r = (Zload - Zsource)/(Zload + Zsource)
The reflection coefficient defines the proportion of the signal that is reflected as opposed to the amount propagated, a ρ of ±1 indicates that 100% of the signal is reflected and none is absorbed by the load. Note, for high impedance voltage sensing inputs the fact that 100% of the signal is reflected back towards the load does not preclude their ability to detect them, only that if there is no series termination at the driver end the signal will be reflected back and forth along the line until dissipated by the lines resistance. Each time the reflected signal appears back at the load it may be perceived as a new signal by the receiver.
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Critical Spacing
To prevent or minimize cross talk between adjacent or parallel lines a certain minimum spacing between the lines should be maintained. The rule of thumb is to space the traces a minimum of twice the line width from edge to edge to another trace. Modeling it is key! In a series of FPGAs with 200 high-speed lines in and out of the device, with 28 mils between the BGA points, you want to get them as close as you can get them. But how long can they travel together before there is a problem?
To answer this, you need to model it. The allowable length is a function of frequency and of mismatch. If the receiver and transmitter are not matched to the line impedance or the line is not properly terminated, it can turn into a filter, coupler, transformer depending on the field distribution and coupling between the two lines. For "low" frequencies, where none of the line lengths approach a ¼ wavelength at the operating or edge frequencies 'best practices' and the eye of an experienced engineer can suffice to insure good signal integrity.
The bottom line is that 'best practices' work up to a few hundred MHz depending on board size and material. Over a few hundred MHz, you have to take into account that 2nd, 3rd and 4th order effects become 1st and 2nd order effects. A few millivolts of cross talk and overshoot can become 100's of millivolts! For very high-speed signals, everything on the board is part of a microwave structure, and needs to be treated and modeled like a microwave circuit. Using a 3D field solver, HFSS, or SPICE to model vias and a tool like Specctraquest to model high-speed traces will insure signal integrity and reduce risks of 'unknown' problems on your board.
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At Nuvation, we have designed a multitude of high-speed traces on complex designs as an integral component of our engineering services. We've successfully completed designs with digital signal speeds up to 10GHz and RF up to 24GHz. Nuvation has invested many hundreds of thousands of dollars in tools, systems, and people to develop a "first-time-right" process flow for these high-speed board designs. We find this process is essential to ensure a clean design, especially since today many boards either can't be cut & jumped or because our Clients can't afford the time and money for an extensive debug/bring-up process.
If you have any questions regarding designing traces, and signal integrity, you can reach me at si@nuvation.com.
In the last part of this series, I will be discussing how vias and stubs affect a high-speed signal.
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Part 1: Lossy Transmission Lines
Nuvation-SI homepage
 Signal Integrity Brochure (PDF)
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