Video Co-Processor Demo System

The Video Virtual Socket Demo System is a platform built to evaluate, test, develop, and benchmark custom video applications. The demo system provides infrastructure to allow rapid prototyping of video applications and products.

The components of the system include the Evaluation Module, Texas Instruments EVM DM642 platform, the Xilinx XEVM642 Virtex-4™ SX-35 FPGA daughter card, the Co-Processor Kit, and a demo 2D 5x5 FIR filter application available from Xilinx and developed by Nuvation.

EVM DM642 Platform

The DM642 platform from Spectrum Digital, showcases TI’s DM642 digital media processor (TMS320DM642). The on-board components include SDRAM, flash, 2 video decoders, 1 video encoder, 2 s-video inputs, Ethernet, mic and headphone jacks, and on-screen display FPGA implementation. The EVM DM642 platform can be customized using TI’s Code Composer Studio.



XEVM642 Virtex 4 Daughter Card

The XEVM642 Virtex-4 SX35 FPGA is a video co-processing development platform from Spectrum Digital, that plugs into the EVM DM642 module, and boasts a Virtex-4 SX35 FPGA for customizable video applications. From video algorithm acceleration and data compression, to filters and custom logic, the powerful Virtex-4 FPGA is easily programmable with Xilinx VHDL/Verilog ISE Design Entry or System Generator for DSP software.


XEVM642 Co-Processor Kit

The Co-Processor Kit comprises of DM642 code, Virtex-4 code, and a PC-based media viewer. With the application code, the demo system is customized to provide a common set of base functions that nearly every video processing application requires. The base architecture removes the overhead of “reinventing the wheel” and allows for rapid prototyping and development of proprietary differentiating video processing functions.

The resulting system acts like a Virtual Socket for video applications, as the user can plug in any custom application for a cost and time effective proof of concept.


Demo Application

Finally, the last component included with the system is the filter application to demonstrate one of many possible functions that can be implemented in the Virtual Socket. The function is a 2D 5x5 FIR filter with selectable rectangular filtering window that allows filtering of the video samples within the processing window, while passing all other samples without processing; the position and size of the window is carefully implemented to allow uninterrupted video streaming during modification.

The filter coefficients are 16bit signed 2’s complement fixed point numbers allowing implementations of high precision video filters with gain. The coefficients are loadable at runtime and are carefully designed to engage without disturbing the video stream. The resulting video is normalized and clamped in accordance with BT.656/601 as a post-processing step in the filter.

The filter demo utilizes 1 video input and 1 video output within the Video Virtual Socket Architecture.

Picture-in-Picture (PiP) Demo

The Picture-in-Picture (PIP) Video Reference Design scales one input video source and inserts it into another using Nuvation demo code with the EVMDM642 and Xilinx/TI daughter card. The output video stream can be seen on a webpage at IP address 10.0.10.105. The PiP demo can be run by downloading the code for the TI DM642 DSP and Xilinx Virtex V2Pro, User Guide, and a viewer to test the PIP video from Nuvation's website .


System Architecture

The hardware architecture of the demo system is shown in Figure 1. The Ethernet connection on the EVM DM642 links to a PC for video output using a custom PC media player.

Figure 1: Video Virtual Socket Demo Architecture

Video Input: one or more video input modules can be present in the system. Each video input will accept standard definition digital component video input in ITU-R BT.656/601 format. Multiple video inputs are supported operating in both 525/29.97 (“NTSC”) and 625/25 (“PAL”) video formats. Each video input can be completely asynchronous to the system video clock (VCLK) and to any other video input. The video block generates a stream of encoded video data and extracts clock and field information.

TPG (Test Pattern Generator): the TPG module generates a simple color bar test pattern to allow design testing and calibration without an external video input.

Multiport Memory Controller: The memory controller provides multiple video channel read/write ports to the system. The frame synchronizer the Memory Controller for the purpose of synchronization and delay. The user function that plugs into the “virtual socket” may utilize additional memory ports as required by the function. The Memory Controller and external SDRAM operate synchronously and at a multiple of the system video clock (VCLK).

Video Output: Multiple video output ports are capable of operating in both 525/29.97 (“NTSC”) and 625/25 (“PAL”) video format modes. Each video output is synchronous to the system video clock (VCLK) and to all other video outputs. It generates standard ITU-R BT.626/601 video streams and also produces V, H, and F output control signals each with programmable phase, width, and polarity.

Host Interface: The host interface module provides an interface to allow control and status interaction with the TI DM642 DSP.

For more information, contact sales@nuvation.com