  The MathStar Arrix Field Programmable Object Array (FPOA) is this issue’s device spotlight. Nuvation has been working with Mathstar since their inception and has been extremely impressed with the technical innovation of their FPOA. The unique object array architecture of the MathStar FPOAs opens up new opportunities not currently accessible via traditional fine-grain FPGA programmable logic devices.
The Arrix Family of Field Programmable Object Arrays is the second generation
of FPOA products from MathStar. A one GHz FPOA delivers up to four times the performance of today’s top FPGAs and combines high performance and re-programmability to meet a wide variety of application needs. FPOAs are comprised of hundreds of objects that pass data and signals to each other through a patented 1 GHz interconnect fabric.
FPOA Features
The Arrix family has the following features:
- 400 Silicon Objects with operation up to 1 GHz
- Two Bi-directional 500MHz DDR 16-bit LVDS ports (64 Gbps of bandwidth)
- 96 pins of LVCMOS GPIO, operating either synchronously or asynchronously up to 100 MHz.
- Twelve banks of 500MHz internal SRAM memory banks (57 GBytes/sec.)
- Two 266 MHz 36-bit DDR (72-bits per cycle) RLDRAM II controllers for external memory accesses (4.8 GBytes/sec.)
Target Applications
The MathStar FPOA is ideally suited for a number of high-performance applications. The FPOA Architecture with its combination of programmability, high performance, high-speed I/O and flexible object array mix makes it well-suited for the following applications
- Professional Video: 4:2:2 high definition encoding and decoding such as: MPEG-2, MPEG-4/H.264 and JPEG 2000. Color space conversion, flat field error correction, 2D filtering and 2D/3D image processing.
- Machine Vision: Image processing, edge detection, object recognition, pattern matching, high resolution cameras, high speed filtering and real-time displays.
- Medical Imaging: 2D and 3D rendering, CT filtered back projection, ultrasound beamforming and high speed filtering.
- Test & Measurement: Multi-channel data processing, signal processing, programmable triggering and real-time displays.
- Military/Aerospace: Sonar, radar, image processing, software defined radio, FFTs, IIRs and/or PolyPhase Filters.
- Signal Processing: Imaging and communications DSP applications which utilize FFT, IIR and FIR filters, adaptive beamforming, 3G cellular basestations, JPEG 2000, MPEG-2 and MPEG-4/H.264.
FPOA Array Structure
 In MathStar's flagship Arrix FPOA, there are three Silicon Object types distributed within the array structure: The Arithmetic Logic Unit (ALU), the Multiply Accumulator (MAC), and the Register File (RF). Additionally, internal RAM is available within the array and external DRAM can be directly connected. The array connects to both high-speed LVDS I/O and general purpose I/O allowing both high bandwidth and flexible I/O configurations. The ratio and placement of different Silicon Objects allow for high-performance Digital Signal Processing applications.
Communication Fabric
 Communication between Silicon Objects is implemented using two mechanisms. First, each Object can transmit to or receive data from each of its eight adjacent objects via Nearest Neighbor connections with zero latency. As the distance between objects increases, Party Line connections provide pipelined connectivity, allowing data transfer at the full core clock rate. For FPOAs operating at 1 GHz, Party Lines connections provide data movement to a distance of up to three objects within a single clock cycle.
Design Flow
 MathStar's Field Programmable Object Array design software enables designers to create, verify, program and debug their algorithms on FPOA devices at a higher level of abstraction than used in FPGAs. Designs are entered and simulated behaviorally using Visual EliteTM from Mentor Graphics. Then they are compiled and mapped into the hardware resources of the FPOA device using MathStar COAST design software. An object code stream is generated and is loaded onto the array via a PROM or through a JTAG interface. FPOA designs have a deterministic timing structure. As such, they are timed only on cycle boundaries of the internal clock with no need for gate-level timing closure. This greatly simplifies the design process, improving productivity and development predictability. MathStar also provides a debug tool to enable designers to analyze their designs, once they have been loaded on the FPOA.
Place & Route
A design is floorplanned and optimized using MathStar's COAST (Connection and ASsignment Tool) software. COAST is a graphical floorplanning editor that allows the designer to assign functional modules to the physical resources of the FPOA. In addition to floorplanning, COAST includes powerful analysis and guidance logic to assist the user. COAST presents the user with graphical representations of the design hierarchy and the array resources. COAST enables designers to alter, upgrade, or optimize existing designs as requirements change during the design process. A variety of predefined library elements are also available to assist the designer.
Conclusion
 The MathStar Arrix family of Field Programmable Objects Arrays delivers up to four times the performance of today’s top FPGAs and combines high performance and re-programmability to meet a wide variety of application needs. Nuvation is a Certified Design Denter for MathStar and has experience with Mathstar devices and tools. We are happy to assist from feasibility analysis and system architecture through design implementation and production release. For more information on integrating MathStar FPOAs into your design applications, contact Nuvation at sales@nuvation.com.
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