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Treating Noise Pollution in your Circuit
Noise analysis and reduction is an imperative step in board design, especially in an environment where electronics are shrinking in size and increasing in density and speed. Let's look at a sample design as is blocked out in Figure 1. We have an incoming analog signal, from either an antenna or cable into a low noise amplifier (LNA), to an anti-aliasing filter, into an analog to digital converter, and then feeding into an FPGA. The FPGA processes the data and produces a digital signal out to a DAC, followed by an amplifier, which sends the output analog signal.
I have identified 3 areas within the circuit that may have noise issues. My goal in this article is to discuss the various types of noise encountered in these three areas, and methods to minimize the noise.
 Johnson Noise, Shot Noise, Flicker Noise
 Clock Jitter, Phase Noise
 Clock Jitter, Metastability
Lets begin...
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Johnson Noise, Shot Noise, Flicker Noise
In general, (Johnson or white noise) is the noise generated by thermal agitation of electrons in a conductor. The amplitude of the noise is dependent on two factors; resistance and temperature. The magnitude of white noise is determined by the following equation, S=4kTR, where T= temperature in Kelvins, R = resistance in Ohms and k= Boltzmans constant. S is noise power in Watts per Hertz. The amplitude of this noise is the same for all frequencies.
Shot Noise is noise created by collisions between charge carriers in a conductor or semiconductor while a current is flowing, its magnitude is proportional to the magnitude of current. This noise product is strongly dependent on the physical nature of the medium.
Flicker Noise also known as pink noise or 1/f noise is generated in semiconductors and other active devices, and as the name indicates, reduces as the frequency increases it has its highest magnitude near 0 Hz.
Additionally, if a general definition of noise is any unwanted signal impinging on the circuit, then additional sources of noise called interference may be injected by poor layout and decoupling choices. Interference includes crosstalk, ground bounce and radiated noise from other parts of the circuit.
The major sources of noise in Figure 1 may also include noise on the input signal, crosstalk and interference resulting from poor practices in the physical layout of the board (parts placement), the types of components used, juxtaposition of traces, and improper impedance matching.
In general, the higher the resistance or impedance, the more thermal noise will be generated. Minimizing impedance is a general goal to reduce thermal noise. Routing a "loud" trace, or a trace containing a fast high amplitude digital signal too close to a "quiet" analog trace will inject noise onto the analog trace.
In addition, not setting up ground return paths correctly will generate unwanted noise. Effects of untreated noise can produce strings of pulses embedded in clean signals. For example, telephone signals can have pops, grinds, and snaps, and video signals will show snow, tearing, and distortion.
To minimize thermal noise, picking the right part to minimize noise figure, and laying out the board with proper design rules is key:
Good grounding: This entails making sure you have the return paths of the signals you're sending directly under the signal trace, ensuring that there are no moats or voids in the ground return path. For high speed or broadband signals, the conducting traces on a PCB form transmission lines. A transmission line is represented by a pair of conductors in exact juxtaposition to maintain the desired impedance. If the two conductors are separated such that a loop forms, two consequences result; first, the loop becomes an antenna that radiates into the space around the conductor, which will impact other devices on the board as well as other nearby electronic equipment. Second, the impedance of the transmission line will not match either the source or load causing reflections on the line that may cause false triggering or damage to the devices connected to the traces The return path for low amplitude analog signal should not cross or parallel a digital signal through the grounds. Digital signals potentially create lots of electrical noise, because of their fast edges; proper design of the signal transmission paths will reduce this noise and may eliminate it entirely.
Parts placement: Proper parts placement involves maintaining the shortest possible path for high frequency or high-speed signals, and planning proper transmission paths. Keeping high noise generating components apart from high-sensitive parts is essential. For example, an FPGA should never be placed next to an LNA. In general, components that switch should be placed as far away as possible from linear analog components.
Impedance Matching: To reduce transmission line effects, drivers and receives should all have the same impedance. If not, reflections will be created on the line that will radiate and may create havoc.
Power Supply De-coupling: Power and ground planes from an AC point of view are the same thing. They are both a return. Minimize AC impedance paths between the power & ground planes. De-coupling around the device itself (close proximity) is key! Using good quality ceramic capacitors, isolating high transient current devices from the power planes using Ferrite beads is essential.
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Clock Jitter, Phase Noise
Clock jitter is the variation in timing of a critical instant in a periodic waveform with respect to a jitter free reference. All oscillators and signal sources exhibit phase noise of some sort. From pulse to pulse the clock edge moves, causing all devices that depend on a reference clock to be skewed in a random fashion. Deterministic jitter is jitter created by a non-stochastic process, which can be calculated and removed. Random jitter follows a Gaussian distribution, and understanding the mechanisms that create it is important so that it can be minimized by proper design practices.
The ADC uses the clock to select points to sample on the incoming analog signal. If there is clock jitter or phase noise in the clock, the sample points will not be uniform and the resulting set of data will not accurately represent the input signal. For example, if the input signal is a sine wave, the jitter in the reference ADC clock will result in a phase modulated sine wave by the amount of jitter. In other words, instead of a single line in the frequency-domain, a spectrum will be created. The captured signal becomes a complex waveform with side bands, instead of a pure sine wave. Now, replacing the sine wave with a real-world complex waveform as the input will result in a far more complex wave, skewed by the phase noise in the clock.
Reducing clock jitter depends on many factors including the design of the clock oscillator and the method of connecting the clock to the device. The maximum non-overtone frequencies provided by a crystal oscillator are around 25 MHz. In most cases, to achieve higher frequencies, the crystal is combined with a multiplier into a third or fifth overtone or harmonic of the crystal's base frequency, and as a result the phase noise/jitter multiplies with the multiplication factor.
Using Phase Locked Loop: One method to achieve higher clock frequencies from a low frequency crystal is the use of a phase locked loop (PLL). A PLL can be used to multiply the clock without multiplying the clock jitter. The PLL consists of a reference source (Crystal Oscillator) Voltage Controlled Oscillator (VCO) a phase detector and digital counter used as a frequency divider. The two most critical elements in the PLL for maintaining low phase noise are the reference and the VCO. The "Q" of the VCO needs to be as high as possible and the VCO tuning range needs to be kept as narrow as possible reducing the amount of phase noise. The control loop voltages need to be kept as clean as possible, generally, a linear regulator and good filtering needs to be employed for powering the components in the PLL.
The use of good general design practices is key:
Bad power and ground noise contributes to jitter. Power planes moving around or bad ground bounce increases clock jitter. So, once again, de-coupling is very important to get rid of jitter.
Using differential signaling instead of single ended signaling is another key design principle to reduce jitter. There are many advantages to differential signaling. For example, in relation to common mode vs. differential noise, differential signaling causes common mode noise to stay as common mode noise, instead of changing to differential noise in a single ended signal. Within a certain range, the common mode noise in a differential pair will be ignored by the receiver. This significantly minimizes the burden on the signaling path since two signals are present, and there are no flowing ground currents. Differential signals also allow for faster signal speeds, since much lower core voltage levels (< 1 V) can be used.
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Clock Jitter, Metastability
A violation of setup and hold times in a flip-flop may cause the flip-flop to enter a state where the output is unpredictable or at a mid (non digital) value, giving rise to metastability. In a situation where the clock edge and data edge arrive at exactly the same time, the flip-flop can fall into a midstate that stays unresolved for a period of time before it settles back into a "digital" state.
Clock jitter can create metastability, since it may cause violations of the clock setup timing, by causing the clock edge to line up with the data edge. The consequence is to lose data streams for up to several 100ms before the system recovers.
Methods to reduce metastability, include minimizing clock jitter, as outlined in the previous section, and using a pipeline register. The pipeline design is a series of synchronized flip-flops to delay that propagate the signal through the register and insure that the clocks and data are in the proper timing relationship to each other thereby avoiding instability. Metastable events in the first synchronizing flip-flop resolve as they propagate through the pipelined flip-flops. The drawback to this approach is the output data is delayed by one or more clock cycles.
Modern logic devices work fast enough, specifically designed to minimize metastability and metastable intervals to tolerable levels. What they can't do is restore the data lost by setup and hold violations created by excessive clock jitter. If jitter can't be reduced, then the clock speed and data throughput needs to be reduced until the violations don't occur.
In conclusion, I hope this article has been helpful as an introductory primer on low-noise design principles. As densities and circuit speeds increase, we're seeing more companies venture into designs where various types of noise must be minimized. If we can assist with design reviews, system-level signal integrity consulting, or turnkey design realization, please don't hesitate to contact us. I can be reached via si@nuvation.com.
- Ben
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