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PCI Express
Getting in the Express Lane with FPGAs
PCI Express Emergence
PCI has long been the ubiquitous standard for PC interconnect technology. The original 32-bit, 33MHz PCI buses dominated the landscape for many years and are still being designed-in to many embedded system applications where (theoretical) 133MB/sec performance will suffice. As with everything else, the PCI standard has been advanced to faster and faster speeds. 64 bit, 66MHz PCI gave way to PCI-X's 64 bit, 100-133MHz bus speeds (up to 1GB/sec). PCI Express is now positioned as the logical interconnect technology for products being developed today.
PCI-X 2.0 was introduced as a promising next gen, offering backwards compatibility up to 4.3GB/sec. However, the high-speed parallel architecture has not been widely adopted due to a variety of design issues associated with extending these parallel PCI-X variants (large/expensive connectors, signal integrity routing challenges/higher layer counts, etc). Intel's AGP8X parallel graphics bus standard is also being supplanted by PCI Express.
Competing serial interconnect technologies such as HyperTransport and RapidIO were gaining traction but have slowed dramatically with the introduction of PCI Express. PCI Express offers many advantages over HyperTransport and RapidIO for chip-to-chip and board-to-board interconnects. There will be niche markets where alternative serial-link technologies may thrive, but none will have the mass-market adoption of PCI Express. Even AMD, which created the HyperTransport standard, is now backing PCI Express.
About PCI Express Technology
PCI Express is a high-bandwidth, low pin count, serial interconnect technology. PCI Express is not hardware compatible with parallel PCI buses, but it does maintain software compatibility with PCI infrastructure. PCI Express can be implemented in one, two, four, eight, or sixteen lanes. Each lane can carry traffic of 2.5Gbps in one direction.
PCI Express has advanced features that are being phased in as operating system and device support is developed:
Unique power management for high-speed serial interfacing
Real-time data traffic
Hot swapping
Data integrity and error handling
Advanced Switching
PCI Express has "active-state" power management to reduce power consumption. When a PCI Express link goes idle, the link can transition to a low-power state. There is a tradeoff with recovery time to resync the Tx/Rx but the latency and power usage can be optimized to the application.
Real-Time Data Traffic support is designed for applications that require real-time data such as VoIP and real-time video. PCI Express has native support for isochronous data transfers and various QoS levels. These features are implemented in "virtual channels" that can ensure that particular data packets arrive at their destination in a given period of time. There can be multiple virtual channels-each an independent communications session-per lane. In addition, each channel may have a different QoS level.
PCI Express has native support for hot plugging and hot swapping I/O peripherals (telecom/datacom line cards, disk drives, PC cards, etc). No sideband signals are required and a unified software model can be used for all PCI Express form factors.
The link-layer and transaction layer functions make PCI Express suitable for high-availability applications, such as communication equipment and servers. PCI Express also has advanced error reporting and handling to improve fault isolation and recovery solutions.
Advanced Switching
In February of this year, the Advanced Switching Interconnect Special Interest Group (ASI SIG) (www.asi-sig.org), released four protocols to the Advanced Switching specification within PCI Express. Advanced Switching is a switched-interconnect and data-fabric architecture for connecting system boards and components in future products. The new protocol interfaces are specialized methods of moving data in communications applications, including PCI Express encapsulation, simple load/store, simple queuing and simple socket data transport.
PCI Express encapsulation describes the standard tunneling scheme for moving PCI Express packets through an Advanced Switching backplane.
Simple load/store is an extension based on the PCI load/store method for transporting data in many communications applications that require specific addresses.
Simple queuing is a method that utilizes queues, instead of specific addresses, for moving messages between sender and receiver for storage and other communications applications.
Socket data transport enables large blocks of data to be moved directly between memory devices without burdening a CPU in a manner similar to Remote Direct Memory Access; also for storage and other communications applications.
PCI Express Design Options
PCI Express is a relatively new standard, originally named 3GIO and sometimes referred to as Arapahoe (which is actually the standards body behind PCI Express). As such, there are no commercial ASICs available yet; at least not thoroughly field-tested, production quantities. PLX and others are very close though and PCI Express ASIC engineering samples can be had.
Companies are implementing PCI Express architectures today using FPGAs from Xilinx and Altera. PCI Express FPGA cores are available and have been hardware validated. Soft cores also give the advantage of customization such as bridging PCI Express to other protocols, adding other core functions or glue logic, etc. Furthermore, utilizing FPGA cores helps future-proof your design through upgradeability and scalability. For example, since the Advanced Switching specification is just released, expect FPGA-based solutions to come available in the first half of 2005 for product shipments in the second half of 2005.
At a PCB level, the serial architecture is implemented using diff pairs at 2.5GHz frequencies. Nuvation has designed to 5GHz edge tolerances for a particular PCI Express application, but generally the diff pairs at 2.5GHz are reasonable to route provided the designer is comfortable working with RF transmission lines at these frequencies and is following appropriate signal integrity rules and simulations. SPICE modeling is the most common way of simulating multi-GHz circuits. In addition to the SPICE tool flow, Nuvation can simulate all high-speed digital circuits (memories, other buses, etc) using Cadence SPECCTRAQuest. SPECCTRAQuest also offers the advantage of dovetailing into OrCAD/Concept schematic capture tools and Allegro for PCB layout. Regardless of SPECCTRAQuest or SPICE, careful simulations are strongly advised as these circuits cannot be cut & jumped.
Nuvation is a member of the PCI Express Developers Forum. We have developed PCI Express solutions for our clients in both hardware (PCB) and soft IP cores. Nuvation has developed a licensable, 16-lane Physical Layer PCI Express core for an FPGA target which is currently being hardware validated. We also have a fully specified and documented design and verification for a full-scale PCI Express core including Link and Transaction layers.
Nuvation is seeking a lead customer for a full-scale PCI Express implementation (including Link & Transaction Layers, up to 16 lanes, bridging or other customizations available). Perpetual, source-code site-licenses can be negotiated. Please contact us if you have questions about PCI Express or are interested in having a custom PCI Express solution developed for you.
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