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Lattice Certified FPGA Design Center |
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Decreasing Sub-System Integration Time
with SOPC Builder
When designing a new product, we usually start at the top level and decompose the product in a variety of sub-systems, i.e. the mechanicals (the packaging), the hardware (electronics) and the application software. Each of the engineering disciplines works to further decompose their sub-system into smaller sub-systems until the point where these sub-systems can be implemented as a unit task or block of work.
Most design teams want to leverage their expertise developed in prior work and re-use the processors, components and standards that they have been successfully with before. To build in competitive value, however, often requires using or developing new sub-systems that may not easily interconnect with the preferred processor, bus structure or interface standard. All too often the integration of the sub-systems becomes the challenge. While integrating the sub-systems together is necessary to bring product to market, it is not the hallmark of the product. Based on this reality, development teams should be looking for ways to leverage development tools to minimize their time spent integrating components and more time on defining or creating the correct components to integrate.
Altera's SOPC Builder tool is a unique product that assists the hardware development by maximizing the time spent on defining and implementing sub-systems that add value to the product and minimizing the time spent integrating these sub-systems to create a working system. SOPC Builder leverages the tremendous capacity, flexibility and performance available through Altera latest offerings in programmable logic, the Cyclone, Stratix and Stratix II and MAX II device families.
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SOPC Builder
Altera's Quartus II development tool includes the SOPC Builder tool that provides a table-based entry system that captures the processors and peripheral information (Figure 1). Each of the SOPC Builder components listed in the library of components provides a minimum of two files. One file describes the component in some form such as a hardware description language (HDL) like Verilog or VHDL. The other file describes the interface signals, the data path, and the requirements of the peripheral to support data transfers. Based on this information, SOPC Builder generates a switch fabric that contains all of the decode logic, arbitration logic, interrupt control, wait-state control and data-path matching logic, as shown in Figure 2. Through simple GUI entry, new components can be entered and master (processor) - slave (peripheral) access can be changed.
Avalon
Instead of trying to force the whole category of peripherals to fit the same bus standard, SOPC Builder creates a switch fabric, based on the Avalon specification that is optimized for the peripherals used in a particular system. The Avalon specification, available for free from Altera's web-site www.altera.com, was designed to accommodate peripheral development for the system-on-a - programmable chip (SOPC) environment. The specification provides peripheral designers with a basis for describing the address-based read/write ports found in Avalon masters (e.g. microprocessors) and Avalon slaves (e.g. memory, UART, and timer) peripherals. The specification describes transfers between the peripheral and a switch fabric interconnect. Further, its interconnect strategy allows any Avalon master to be connected to any Avalon slave, without a priori knowledge.
The resource requirements to build a general purpose switch fabric that could offer the necessary high degree of flexibility to allow any component to connect another component, would be massive and thus cost prohibitive. By using an optimized switch fabric interconnect strategy, however, each peripheral can be developed to exchange data with a switch fabric. In doing so, the burden of generating the appropriate logic to connect the various devices is moved from the engineer to the tool. As a result, the switch fabric approach, allows designers to focus most of their efforts into optimizing the peripheral and its application-the real value of the system-and minimizes the time spent focused on resolving intergration issues. It also helps minimize the amount of peripheral real estate devoted to resolving interconnect compliance issues.
User Defined Peripherals
As with most systems, there may not be a standard product available that exactly matches the requirements. The engineering team must design these specialized components. SOPC Builder fully supports user-defined components through its Interface-to-User-Logic Wizard (Figure 3). The wizard imports the users design file (or files) to read the port list. The user simply maps the port names to equivalent Avalon signals. Most signals are available asserted high or asserted low. Once the mapping is complete, the designer selects the timing page to define the number of clocks required for read and write transactions. This information is sufficient for SOPC Builder to create the appropriate switch fabric and any necessary integration logic to allow any master peripheral to exchange data with the slave peripheral. By publishing the component to the library of components, this component is available for easy re-use in the same system or other new systems without making any changes to the peripheral.
Simplifying Multi-Master Processor Design
The switch fabric approach also makes it simpler to design in multi-master capabilities. There are two ways to interface multiple processors-through either host-side or slave- side arbitration. Using host-side, shared bus access to the peripherals limits system performance since when one master is accessing the bus, other masters must wait until the preceding transaction is completed. With slave-side arbitration, each master has a set of peripherals to which it has sole access and another set of shared peripherals. In these cases, a master is stalled only when another master is accessing the same peripheral. No stalls occur, however, if the two masters access different shared peripherals.
When data needs to move from memory to a peripheral, a slave-side arbitrated system can prove to be very beneficial, as can the use of SOPC Builder. In this case, the data throughput can be optimized by balancing access and the use of direct memory access (DMA) controllers. In contrast to a manual approach, SOPC Builder provides the designer with a table that shows all the processors and peripherals in the system and which processors have access to which peripherals. The peripheral sharing is controlled simply with the push of a button. Each time an adjustment is desired, the designer simply revisits the table, makes the changes, pushes the button and a new optimal solution is generated. Figure 2 shows a system using a processor and DMA Controller working together to move data through the fabric to a video display. In this implementation, the DMA controller moves data from a 32-bit memory to 8-bit wide FIFO buffer in the VGA controller. To do this manually, would entail some amount of time creating and debugging the logic to move the data and manage the flow control.. With SOPC Builder, the single 32-bit read transaction from the memory is automatically converted into four 8-bit write transactions to the FIFO in the Avalon switch fabric. Flow control is managed through the peripherals support for streaming transfers.
Embedded Application Software
Getting the components integrated begins the software development process. SOPC Builder also assists in this area. During system definition, the location and span of each peripheral is specified. Prior to software development, the software engineer needs to this information. Many of the SOPC Builder components include software drivers and sample application code for exercising the peripherals. SOPC Builder copies this software into a software directory and generates a standard C header file with the register declarations and memory. Each time the SOPC Builder generates a system, these files are updated. This continuous hand-off of the latest parameters and declarations with each new hardware image to the software team reduces the time to debug the hardware to software sub-system integration.
Conclusion
Using the latest technology for performing system level integration, tools such as SOPC Builder, provides designers with the opportunity to maximize their time on the most valuable portions of the system by spending less of their time on the integrating the sub-systems. SOPC Builder is a unique productivity enhancing tool that leverages the density, features, and performance of today's CPLDs and FPGAs, to implement a novel switch fabric interconnect methodology. This approach also provides further opportunities to increase the system's performance and to add additional capabilities into the system. SOPC Builder is available only from Altera in Quartus II development tool subscription product as well as Quartus II web-edition which is available for free from Altera's web-site www.altera.com.
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