The IPFlex DAPDNA-2 is this issue’s Device Spotlight.  Their second generation dynamically reconfigurable processor, the DAPDNA architecture is a programmable logic device with ultra high-speed processing.  To cut to the chase, the dynamic reconfiguration really sets this device apart.  In a single clock cycle – 6 nanoseconds – the entire device can reprogram to run a completely different algorithm.  This changes the landscape for bringing reconfigurable computing into the mainstream.  For example, a single chip can handle multiple phases of a large algorithm, a DAPDNA coprocessor can now load and unload dedicated processing hardware with the ease of memory, and a chip could even monitor and self-heal itself instantly.

This isn’t some startup pushing vaporware either.  IP Flex has over 20 volume design wins in Japan, and now wants to bring this technology to North American markets.  The next Achilles heel that kills most fabless semiconductor startups is lousy tool support.  To our pleasant surprise, when we evaluated the DAPDNA tool chain we found a package that allowed you to both design in a top level “C-like” language and go all the way down to the floorplanner and tweak the device routing.  Don’t get me wrong – we don’t want to be manually routing programmable logic, and IP Flex assures us that is very rare.  However, when pushing the limits of programmable logic it’s good to know it’s not hidden behind some abstracted compiler curtain, and we have actually have full access to that level of flexibility and control.

The DAPDNA version of C is called Data Flow C (DFC) and provides some logical and productive structures for implementing hardware parallelism and other hardware constructs in a high level language.  There’s also the DNA Blockset, which allows algorithm design and verification using MATLAB and Simulink.  The tools go further to provide waveform viewers, timing chart viewers, memory viewer, resource manager and even power consumption viewer.  Further, the routing is done with a guaranteed clock speed, thus removing the risk of closing timing during place and route.  All in all, an impressive reconfigurable processor backed by a pretty complete toolsuite.

DAPDNA is particularly well suited for short-run mixed-model production.  Application areas include:

• Industrial-performance image processing applications
• Industrial image processing (for factory automation, inspection systems, etc.)
• Broadcast equipment
• Medical equipment (ultrasound, CT, X-ray, etc.)
• High precision, high-speed image processing (multi-function printers, etc.)
• Large-scale industrial printers and copiers
• Base transmission stations (cellular, PHS, etc.)
• Network security appliances, encryption accelerators
• Accelerators for image processing, data processing, and scientific and technical computation
• Software defined radio

The market has an insatiable demand for processing power, and IPFlex will continue to respond with dynamically reconfigurable processors. The DAPDNA architecture is extremely compelling for resource efficiency on multi-phase and multi-granularity algorithms that can reconfigure mid-calculation.  IPFlex's DAPDNA product line dovetails with Nuvation's Algorithm Acceleration services, whereby customers enjoy customized hardware acceleration to generate from 20 times to 100 times performance improvement of software algorithms.  We look forward to many successful co-developments with IPFlex and our North American clients.

P.S. If you’re curious, DAPDNA stands for Digital Application Processor/Distributed Network Architecture.  www.ipflex.com

For more information or a free consultation contact Nuvation.