Nuvation is rolling out an Actel-based ATA-5 IP core this summer. In addition to Nuvation's line of interface cores for various platforms including Xilinx and Altera (SOPC Builder), the new Actel ATA-5 core is currently being validated in a Rad-Hard RTAX2000 for an aerospace application. The core is being used to image data to a solid state disk drive. For more information on the ATA-4 or ATA-5 cores in an Actel device, please contact us.

IP Cores are extremely popular with our customers, greatly accelerating product development cycles and reducing NRE with plug & play solutions. Below is a list of Nuvation's IP cores.


Interface Cores

ATA-4/5 Host Controllers for Xilinx and Altera
ATA-4 and ATA-5 host controller cores were introduced in early 2004 and have been hardware validated with our test platforms and with licensee products. ATA-4 and -5 are commonly used to connect hard disk drives (HDDs) or Compact Flash (CF) devices wherever an FPGA is already present and has spare resources available. Medical imaging, scientific, set top boxes, digital video recorders, surveillance systems, RAID servers, defense-related embedded systems, professional video systems, and other systems that use low-cost FPGAs can benefit from Nuvation ATA cores. We frequently see our IP integrated with PCI and/or embedded processors.

ATA-4/5 for SOPC Builder™
For those who have discovered the ease of use in Altera’s SOPC Builder™ tool for integrating IP with soft processors, Nuvation offers both ATA-4 and ATA-5 cores for SOPC Builder™.  The cores, featuring Avalon interfaces, are specially designed to 'plug & play' with Altera SOPC Builder and a the Nios Development Kit.  The detailed User Guide steps a user through each stage of developing a SOPC Builder™ peripheral and even includes instructions for implementing it in hardware.  Evaluation versions are available now and can be accessed from SOPC Builder's™ web interface. 

SATA Host Controllers
Serial ATA (SATA) is becoming more mainstream for higher throughput data rates. Many of our ATA-4/5 clients are anticipating migration in next-gen designs and many new clients, especially for video storage, can benefit by adding SATA to an existing FPGA. Nuvation has developed and introduced a SATA Host Controller with Avalon interface, for Altera SOPC BuilderTM or Quartus tool flows. We are also making Xilinx Spartan-3/3E and Virtex-4 versions available with an 8 week lead time. Please contact Nuvation for more information on our SATA Host Controller IP Cores.


Telecom/Datacom IP

GEOS Family (Gigabit Ethernet Over SONET)
Nuvation's GEOS cores mux GbE data to/from SONET. We have OC-192 (10Gbps) and OC-48 (2.488Gbps) variants. GEOS cores are designed to interface between the GbE MAC/PHY and SONET Framer chips. The GEOS cores are packed with features such as GFP framing/de-framing, traffic statistics per port, CPU interface, configurable destination addresses, and jumbo packet handling up to 100% bandwidth of 9.6K packets. Our new GEOS 2+2 (OC-48) fits in a sub-$50 FPGA, carrying more bandwidth and at a lower price than competing ASSP solutions. GEOS-8 and GEOS-10 (OC-192) continue to attract new licensees.

GFP-F/T
The GEOS cores include General Framing Procedure (GFP) IP. We have some customers that require GFP but not the full functionality of GEOS (i.e. 10GbE XAUI to SONET). Frame-mapped GFP is used in GEOS (GFP-F) and is licensable today as a standalone core. Transparent-mode GFP (GFP-T) is used in low-latency networking environments (typically FibreChannel) and is available on a 12 week lead time.

DOS Family (Data Over SONET)
As FPGAs continue to increase in density and resources, we have advanced GEOS to include the MAC functionality. Both Ethernet or FibreChannel (FC) MACs are supported, The MACs are available from MoreThanIP for Altera targets. Nuvation IP can also be ported to the new Lattice SC devices with hard IP MACs. We can integrate various combinations of 10/100/1000 Ethernet MACs and 1/2G FC MACs with our GEOS engine and GFP-F and GFP-T cores. Other IP can be integrated as well for specialized applications such as broadcast video. The combinations are endless, which is a great advantage over rigid ASSP solutions.


Video IP

Nuvation's IP design team includes many senior engineers with extensive video processing backgrounds.. Our first release is a downloadable reference design for Picture-in-Picture with Xilinx FPGA and TI DM642 DSP co-processing architectures. We are currently introducing another reference design on this platform called Virtual Socket Adapter which enables rapid development cycles for integrating video algorithms from MATLAB/Simulink through Xilinx System Generator and TI Code Composer Studio. Nuvation has other confidential Video IP designs currently underway. If you are a developer of broadcast or consumer video products and have IP requirements that are not currently being served, please contact us and we can discuss our mutual roadmaps under NDA.