The device configuration is stored in non-volatile FLASH cell arrays distributed within the FPGA device.  At power-up, the configuration is transferred from FLASH memory to configuration SRAM in less than 1mS (worst case on largest device) providing an instant-on FPGA.  In addition, LatticeXP FPGA devices provide security by eliminating the need for an external configuration bit-stream and by providing non-volatile security features.

On the downside, there is a small performance hit with no 3G SERDES or 10G throughput, however the Lattice XP is suitable for most applications in cost sensitive markets like consumer electronics, automotive, medical & industrial, networking and computing.

On the upside, the LatticeXP is available at a very low cost in TQFP & PQFP packages.  The device has a 1.2V core, which through on-chip regulation will support Vcc input from 1.2V, 1.8V, 2.5V or 3.3V power supplies. This is beneficial when replacing older CPLD, FPGA, ASSP, ASIC devices which have legacy voltage requirements, therefore providing obsolescence protection and design scalability.  It supports LVCMOS, LVTTL, PCI, LVDS, SSTL, HSTL and up to 4 analog PLLs. In addition, the LatticeXP has dedicated circuitry to simplify DDR (up to 166MHz/333Mbps) memory interfaces.

LatticeXP is supported by the ispLEVER design tool suite. Lattice ispLEVER software includes synthesis support using Mentor Graphics Precision RTL and Synplicity Synplify design tools. An extensive range of IP (intellectual property) cores, particularly suited for high-volume applications, is available from both Lattice and its IP partners.