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| Summer 2005 | Frontpage | Subscribe | Feedback | ||
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Benefits of Utilizing an FPGA to Structured ASIC Design Flow
According to the Fabless Semiconductor Association (FSA), a 90-nm ASIC can cost $30 million to develop. Add expenses associated with intellectual property (IP) development, and a company roughly needs a $1.5 billion target market to justify a product. Field programmable gate arrays (FPGAs) provide some relief when compared to standard-cell ASICs; design changes can be implemented using the same FPGA until the final working solution is reached—a significant cost-saving benefit not available with standard-cell ASICs. While FPGAs can be used for ASIC prototyping, using standard-cell ASICs or application specific standard products (ASSPs) for volume production has historically been the preferred path for many device manufacturers. Structured ASICs provide a solution for high-volume production at less risk than standard-cell ASICs. Conceived to bridge the gap between standard-cell ASIC technology and FPGAs, these devices feature standard-cell ASIC-like performance at low unit costs combined with faster development times. Some structured ASICs, however, require lengthy design verification time and simulation to reduce the risk of design problems, and even then the design cannot be fully validated until the prototypes are manufactured. What has been missing is a structured ASIC design process that reduces time-to-market while still allowing ASIC and ASSP designers to use their existing design environments, including those provided by electronic design automation (EDA) vendors. Once finalized, the design could then migrate to the structured ASIC for high-volume production. Altera’s HardCopy ® design process provides such a solution. A semiconductor industry first, the HardCopy process enables designers to target a structured ASIC from the beginning of a design cycle, seamlessly migrating the design from one device to another to minimize risks. After prototyping and early production with a FPGA, the design migrates to the HardCopy structured ASIC for volume production. By using FPGAs at the front end, an engineer can use EDA software to create, test and verify a design, hand it over to an electronic design services (EDS) firm such as Nuvation for design optimization and floor planning, and then let Altera implement the design in HardCopy structured ASICs. This design process supports seamless migration from the FPGA prototype to structured ASICs with pin-to-pin compatibility. Designers do not need to redesign the board or redevelop and revalidate the system, resulting in significant cost savings and time-to-market benefits. ASIC and ASSP designers can take advantage of process integration between FPGA vendors such as Altera and Nuvation for system-level design and concurrent hardware/software design. They can also use it for testing a product in the field prior to production to take care of debugging in a Stratix II FPGA prototype, then migrate to a HardCopy II structured ASIC with guaranteed design success. This design path is possible not only because of the precise pin-to-pin compatibility and design process, but also due to equivalent clock networks, I/O buffers, PLLs and memory blocks, between the Stratix II FPGA and HardCopy II structured ASIC. Altera’s HardCopy II structured ASICs and Quartus II design software enable system designers who utilize EDA tools to continue using those products in unison with the Altera solution for critical cost control throughout the design-to-production process. An Altera/Nuvation solution can provide a complete front-to-back strategy for HardCopy II, with Nuvation optimizing your IP blocks for Altera devices. Cognizant of meeting the design demands of its customers, design teams can opt to design for the flexibility afforded by Altera ’ s FPGA prototype-to-structured ASIC migration solution because it enables them to easily create customized designs according to individual customer specifications. Using FPGAs for ASIC or ASSP prototyping and then migrating to structured ASICs for production can help reduce non-recurring engineering costs (NREs), including design, layout and verification, associated with these devices continue to rise as designs migrate to smaller geometry technologies . By using a trained and certified EDS company such as Nuvation, these design teams can help save costs while maintaining the high engineering levels required for Altera ’ s technology. Conclusion: Designers who traditionally have used ASICs and ASSPs for volume production due to their high performance and cost effectiveness now have another option that combines the design flexibility and high performance of FPGAs with the time-to-market benefits of structured ASICs: Altera's HardCopy solution. When using a FPGA/design software package, including proprietary EDA tools, at the front end and HardCopy at the back end within a seamless migration, designers can realize an effective design-to-production process at a significant cost reduction when compared to ASIC or ASSP devices.
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