Cyclone III FPGAs are designed for high performance, low power and low cost applications and can be used in all areas where these factors are critically important. Most frequent applications include:

• Display of all sizes
• Video and Image Processing
• Wired and Wireless Communications

Family Highlights

1. Includes largest low-cost FPGA (the 120K-logic element EP3C120)
2. Only 65-nm FPGA family optimized for lowest power (the largest device consumes only 200 mW standby power)
3. All family members supported in the free Altera’s Quartus II web edition software

The Cyclone III family consists of eight devices ranging from 5K to 120K LEs (logic elements) and up to 535 user I/O pins. These devices are available in eight different package options, with varying available resources, summarized in the following table.

The main characteristics of Cyclone III FPGA devices are discussed below:


Clocking

Cyclone III FPGAs have up to sixteen dedicated clock input pins that feed the global clock network lines directly. The global clock network in Cyclone III FPGAs consists of twenty global clock lines accessible throughout the entire device. It is optimized to minimize skew, providing Clock, Clear and Reset signals to all resources inside the FPGA.

The PLLs inside Cyclone III FPGAs provide general-purpose clocking management capabilities such as multiplication and phase shifting, programmable duty cycle, programmable bandwidth, spread spectrum input clocking, lock detection, as well as outputs for differential I/O support. Each PLL has one external clock output that can be used to provide clocks to other devices in the system. This eliminates the need for other clock-management devices on the board. 

Cyclone III PLLs can be dynamically reconfigured to enable auto-calibration of external memory interfaces while the device is in operation. This feature also enables support of multiple input source frequencies and corresponding multiplication, division, and phase shift requirements. PLLs in Cyclone III devices may be cascaded to generate up to 10 internal clocks and 2 external clocks on output pins from a single external clock source.


Embedded Memory Blocks

The embedded memory consists of columns of 9-Kbit (M9K) RAM blocks, each capable of data transfer rates up to 260 MHz. These embedded blocks can be used to implement various kinds of memory that include single-port and dual-port RAM, ROM and FIFO (first-in first-out) buffers. Each block also includes extra parity bits for error control, mixed-width mode, and mixed-clock mode support.

Figure 1: Cyclone III Floorplan Source: Altera

External Memory Interface

Cyclone III FPGAs support dedicated, speed-optimized circuitry to interface with SDR (single data rate), DDR (double data rate) and DDR2 SDRAM devices and QDRII SRAM devices at up to 400 Mbps with an auto-calibrating PHY for fast timing closure.


Multipliers

All cyclone III FPGAs contain significant number of 18 x 18 multipliers. These embedded multipliers can also be configured as 9 x 9. This means a single 18 x 18 multiplier can be converted into two 9 x 9 multipliers. With this amount of multipliers, Cyclone III FPGAs are good candidates to be used in cost sensitive DSP applications.


I/O Standards

Cyclone III FPGAs support a variety of single-ended I/O standards including LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X. Single-ended I/O standards provide more current drive capacity than differential I/O standards, and they are critical when working with advanced memory devices such as DDR, and DDR2 SDRAM and QDRII SRAM devices. Cyclone III FPGAs also support a programmable drive strength control for certain I/O standards with settings ranging from 2 mA up to 16 mA.

Cyclone III FPGAs provide support for LVDS, mini-LVDS, RSDS, and LVPECL. LVDS performance is 840 Mbps for transmit data and 875 Mbps for receive data. On the transmission side, Cyclone III FPGAs do not require an external resistor network to convert the output to the appropriate LVDS swing levels.


Power Supply

Cyclone III FPGAs require a minimum of two power supplies on board: one for VCCINT (1.2 V), and one for VCCA (2.5V).  Another power supply is needed for VCCIO for driving voltages other than 1.2 or 2.5 (3.3 V, 3.0V, 1.8 V, or 1.5 V) which is user-configurable.


Configuration

Altera offers four serial configuration devices (1-Mbit, 4-Mbit, 16-Mbit, and 64-Mbit) in 8-pin and 16-pin SOIC (small outlined integrated circuit) packages.  Four Cyclone III FPGAs also support configuration using industry standard parallel flash devices from Intel and Spansion without the need for an external host.


Pin Compatibility

Cyclone III FPGAs are not pin-compatible with Cyclone II or Cyclone FPGAs.


Design Software

Altera Quartus II 7.0 subscription software and free Quartus II Web Edition 7.0 supports designs targeted on Cyclone III FPGAs. This include updates in SOPC Builder System, NIOS II embedded processor family, TimeQuest timing analyzer and SDC (Synopsys Design Constraints) timing constraints to provide full design environment for Cyclone III FPGAs to the designers.  Programming file generation is supported for the devices that are currently released (the 3C25 and 3C120).  Altera will release software upgrades to support programming file generation for the other Cyclone III family members as they are released. 

Synthesis and simulation tools from leading EDA vendors like Cadence, Mentor Graphics, Synopsys, and Synplicity also support Cyclone III device family.


IP Cores

Several IP cores optimized for Cyclone III FPGAs are available from Altera and its AMPP (Altera Megafunction Partners Program) partners. This includes Nios II Embedded Processor, Video and Image Processing Suite of nine commonly used IP functions, FFT/IFFT, PCI Compiler, FIR Compiler, NCO Compiler, POS-PHY Compiler, Reed Solomon Compiler and Viterbi Compiler. Nuvation’s ATA-4 and ATA-5 Host Controllers are available for Cyclone III, and Nuvation’s SATA, GEOS 2+2 (Ethernet over SONET), and GFP-F/T cores can be made available on-demand.


Availability

The EP3C25 and EP3C120 Cyclone III devices are now available. All the other members of the family will be available by the end of 2007.

For more information, visit http://www.altera.com/products/devices/cyclone3. If we can assist with your  hardware design with Cyclone III FPGA, please contact Nuvation at sales@nuvation.com.

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