Evaluation: Timing Closure with Altera's TimeQuest

Post-place & route timing problems are a growing challenge for FPGA designers. As device densities and design methodologies improve, designers need sophisticated tools to get out of timing trouble. One of the more recent tools is Altera’s® TimeQuest, an ASIC-strength timing analysis tool included in Quartus® II. TimeQuest runs on either a post-map or post-fit database, and produces a variety of detailed reports about timing errors.

Nuvation recently used TimeQuest on a Altera Stratix II GX design project. This design had 19 different clock domains, including a recovered PCIe clock and a recovered XAUI clock. The complexity of the design suggested that timing closure would be an issue, making it a good test case for TimeQuest. Indeed, the initial place & route turned up a long list of timing errors, including Setup, Hold, Recovery, and Removal errors.

TimeQuest can be launched from Quartus II, run as a stand-alone tool, or used in a command-line mode as part of a scripted tool flows. To launch the tool from Quartus II, select TimeQuest from the Tools menu or click the red clock icon in the tool tray. When you launch the TimeQuest directly from Quartus II, the current project opens by default.

The first step in using TimeQuest is creating a Synopsys Design Constraints file (SDC). This file can be written before the initial synthesis, or it can be generated from TimeQuest using the Quartus Settings File (QSF). For our Stratix II GX project, we generated the SDC from TimeQuest. This file provided a good starting point, but the SDC required manual additions to achieve complete timing constraint coverage. For example, it was necessary to define false timing paths.

As illustrated in Figure 1, the TimeQuest GUI Window is divided into several panes. The left side has two panes, Report and Tasks. Tasks perform an operation whose results can be accessed from the Report pane. TimeQuest offers preprogrammed Tasks, and it is also possible to create custom timing reports. The Tasks are partitioned into Netlist Setup and Reports.


Figure 1. The TimeQuest GUI is divided into panes. The Tasks and Reports panes are shown on the left. Tasks perform an operation whose results can be accessed from the Report pane. In this figure, TimeQuest has generated a summary of Hold errors. (Click image to enlarge.)

The next step - one that must be repeated for each subsequent synthesis run - is to create the timing database. This is done with the following three tasks in Netlist Setup:

1. Create Timing Netlist
2. Read SDC File
3. Update Timing Netlist

The Reports pane is divided into Individual Reports, Custom Reports, and Macros. The Macros are a good place to start, as they provide a useful global perspective. The Macro Report All Summaries will give you an idea of how much work lies ahead of you. It’s not unusual to have a wide variety of timing violations at this point. A summary of the violations can be viewed in the Report pane.

Staying with the global perspective, a good next step is to look at the unconstrained paths. The task Report Unconstrained Paths is found under the Reports section in the Task pane. The results of this task are again found in the Report pane. Pay particular attention to any illegal or unconstrained clocks. These must be fixed before the timing analysis is meaningful.

At this point it is likely that the SDC file and RTL have been modified. Changes to the SDC file must be re-read into TimeQuest, and the timing netlist must be updated. Changes to the RTL require a new round of synthesis, place & route, and loading into TimeQuest.

Once the clock and other constraints are acceptable, it’s time to look at specific failing paths. The Macro Report Top Failing Paths allows you to see the worst timing violations. As shown in Figure 2, each violation can be further examined as a path summary, as a complete cell to cell data path, or as a waveform display. This feature is invaluable for identifying whether the timing violation was due to routing delay, too many logic inversions, or a false path. If the latter, TimeQuest makes it simple to set a false path between nodes or between clocks.


Figure 2. Each violation can be viewed as a path summary (top pane), as a data path (middle panes), or as a waveform (right pane). (Click image to enlarge.)

Each Task is performed by a set of TCL commands. The bottom pane of the GUI displays the TCL commands executed when a Task is performed. This is a useful feature, as it allows the user to copy commands for their own use. For example, you can copy the commands for setting a false path into the SDC file. This gives the next synthesis run knowledge of the false path, and helps it do a better job of fitting.

Assuming that the RTL coding was done using good synchronous design practices, the timing violations can usually be fixed in a few iterations. In the case of the Stratix II GX project, the timing failures were reduced to a few set-up violations in just three iterations. Resolving these remaining violations required some floor planning.

I found TimeQuest to be a very intuitive and simple-to-use static timing analysis tool. Regarding its accuracy, I can report that the Stratix II GX project with PCIe and 10 gigabit Ethernet MAC came up on the PC Board and worked first time at full speed.

Additional information on TimeQuest can be found on Altera’s web site at http://www.altera.com/support/software/timequest/sof-qts-timequest.html.