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Ethernet-over-SONET Solutions for Metro Area Networking
(with up to a 10-Gbps Data Rate)
There is an increasing demand for Ethernet traffic over metropolitan area networks (MANs). Since their infrastructures are not geared towards packet-switched traffic (e.g., Ethernet), carriers are now struggling to provide this service capability. In recent years, these carriers have invested a large amount of capital in creating the time-do-main multiplexing (TDM) infrastructure (e.g., circuit-switched oriented SONET) to provide voice and private-line connections.
The most cost-effective solution for providing Ethernet services is to transport it over the existing infrastructure to make use of the capital already invested-transport Ethernet traffic (packet-switched) over SONET (circuit-switched) equipment.
For instance, consider a special case of Ethernet-over-SONET (EoS) equipment. In this case, the EoS equipment is required to transport up to 10 ports of Gigabit Ethernet traffic by connecting to a SONET ring. An optimal solution is to aggregate the traffic from all gigabit Ethernet ports into a single 10-gigabit per second (Gbps) SONET pipe (e.g., OC-192). The traffic aggregation requires all EoS equipment to adopt a standard protocol, such as generic framing procedure (GFP), to de-multiplex the traffic at the destination.
To design such equipment, one would have to choose a number of system components. The major system components are listed below.
Serializer/deserializer (SERDES) devices for gigabit Ethernet ports
MAC/PHY devices for handling Ethernet traffic
A device for aggregation and GFP protocol implementation
SONET framer
SONET optical module
SERDES, MAC/PHY, SONET framer, and SONET optical modules are available from a number of well-known companies such as Intel and PMC Sierra. Designers can implement a GFP protocol in an FPGA (a GFP protocol is required to interface the MAC and SONET framer). Altera Stratix FPGAs handle traffic aggregation and GFP protocol implementation, as shown in Figure 1.
Figure 1: GEOS Core in a Stratix Device
The Stratix device interfaces to the MAC/PHY and SONET framer devices using the SPI4.2 interface specification from the Optical Internet-working Forum (OIF). This interface uses a 16-bit double data rate (DDR) with a clock rate of up to 400 MHz, making it capable of handling over 10-Gbps data rates.
The internal components of the Stratix device are readily accessible through easy-to-use Altera megafunctions. You can implement Stratix devices using two types of intellectual property (IP) cores: POS-PHY Level 4 and GEOS. The POS-PHY Level 4 IP core facilitates interfacing to the SPI4.2 bus for application-specific implementations in the Stratix device. The GEOS IP core implements the GFP protocol in addition to traffic aggregation. Additionally, GEOS implements features such as full-duplex pause flow control and Ethernet jumbo frame transport over SONET.
The POS-PHY Level 4 IP core is available through Altera, and the GEOS IP core is available through Nuvation.
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