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FPGA Configuration
Simple, Inexpensive, and PCB Real-Estate friendly
Board designs today are often utilizing several large programmable logic devices (PLDs, ranging in size from relatively small CPLDs to larger FPGAs). In these multi-PLD designs, the FPGA configuration scheme can become a major factor. When dealing with a single, large FPGA, configuration can be done with a single CPLD plus FLASH device or a vendor-specific FPGA configuration PROM device. This requires minimal board space and little cost impact. When one extends that scheme to several FPGAs, cost and board space impacts increase significantly.
The problem becomes even more exacerbated when incorporating soft-processors in FPGAs. Then you've likely got two configuration cycles for each FPGA/embedded MCU (one for the FPGA, then a boot cycle for the embedded processor), and possibly even more space needs (you may need larger flash devices). Now what if you also want to be able to reprogram all of the FPGAs and embedded processors through a communications interface? Then you're also dealing with N communication interfaces for N devices. These problems are starting to pile up.
A separate processor could solve the problem, handling the communications and the configuration, but now we're adding more board components. And on top of all this, you've got to consider constraints on board space, design complexity, and field serviceability needs. So how does one solve this problem?
The solution is to do more with what you've got, in this technique you'll even use fewer chips in the process. The first step is to centralize the FPGA and processor configuration code to a single chip; using a single CPLD for initial startup and one of the FPGAs with an embedded processor to configure the other FPGAs (along with their processors). The result is a reduction in board space requirements, but it definitely adds some design complexity. That's where Nuvation's Embedded Configurator comes to the rescue, as we've already solved this challenge for you.
Nuvation's Embedded Configurator works in general as previously described - a single FLASH device for all the configuration images, a single CPLD for startup, and no additional external processor. We've implemented this system using a NIOS processor, a CPLD with no special requirements, and a single 8MB FLASH part. The overall system works by identifying a single FPGA as the configuration master. This part boots first, using the CPLD and the first FPGA and the processor configuration image from the FLASH. Once the configuration master is booted, the NIOS kicks in and takes over the FLASH bus from the CPLD. Each of the other FPGAs is the configured sequentially by the NIOS over a passive serial interface.
The images come from the same FLASH device, and the passive serial interface is built as an SOPC (System On Programmable Chip) peripheral. In our hardware validation environment, each of the slave FPGAs was configured with a basic NIOS build inside the configuration image, which then boots along with the FPGA, requiring no outside code. This basic NIOS build has a serial port link back to the configuration master. Once the FPGAs and the basic NIOS's are booted, the configuration master then uses the serial links to download full NIOS code builds to each of the FPGAs. At the end of this sequence the configuration master then triggers a self-reconfiguration using the CPLD, loading an alternate FPGA bitstream. This avoids wasting resources from the configuration system during run-time operations.
One of the key advantages of the Embedded Configurator is that it uses almost entirely off-the-shelf configuration solutions along with a re-usable SOPC Peripheral and the associated code. The only modifications required are some changes to the CPLD and some changes to the bootrom for the configuration master's NIOS. The slave NIOS's are default instances of the bootrom, accepting boot code over the serial link in the same way it is delivered in the development tools from Altera. Between the serial link and the passive serial configuration link, the required inter-FPGA connections are very minimal, and can be reclaimed after configuration for other uses.
This system is based around a design concept and code that is hardware-validated and reusable. The hardware-validation was done on a board with 5 Altera Stratix 1S80's, 1 Altera 1SGX25, a Xilinx Coolrunner CPLD, and one 8MB AMD FLASH device. Nuvation will be releasing the passive serial configuration SOPC Peripheral in Q2, though for specific customer engagements it can be made available today. For questions please email Nuvation at ip@nuvation.com.
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