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The SI FAQ
Signal Integrity Analysis Explained
 About me: Ben Schramm
Signal Integrity at Nuvation
When should I consider SI analysis?
How do I get started with Nuvation-SI?
What tool flows do you use, how, and when?
What about DFT?
What do you recommend for PCB fab materials and vendors?
Who should do layout?
What is Post-Layout SI?
What should I expect as a result of using Nuvation-SI?
What if I only need some basic consultation?
How can I reach Nuvation-SI?
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About me: Ben Schramm
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  For those of you who may not yet know me yet, I've been doing 20+ GHz designs since long before we had all these fancy computer-aided design tools. My professional experience began as a microwave engineer working on electronic warfare IFF, automatic fire control systems, and satellite Laser and Microwave communications systems. Later I spent a decade or so in Medical MRI and Ultrasound systems. In the past few years here at Nuvation, I've been directly or peripherally involved in hundreds of interesting projects spanning just about every market. In brief, I have more decades of experience than I care to admit designing circuits that cover the entire spectrum from DC (power supply and audio design) to Daylight (microwave to 24GHz, YAG, CO2 and Doubled YAG lasers). Here at Nuvation I lead a small but gifted team of analog and digital-SI engineers and work with a truly great team of senior engineers in a variety of disciplines such as digital electronics, digital signal processing, FPGA design, and firmware for MCUs, NPUs and DSPs.
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Signal Integrity at Nuvation
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At Nuvation, we've been performing SI analysis on complex designs for years as an integral component of our standard "concept-to-production" engineering services. We've successfully completed numerous first-time-right designs with 'digital' signal speeds up to 3.125GHz. We also have tackled many other complex projects involving ultra-high-density, ultra-low-noise, precision analog, custom power, and RF up to 24GHz. Nuvation has invested many hundreds of thousands of dollars in tools, systems, and people to develop a "first-time-right" process flow for these complex board designs. We find this process is essential to ensure a clean design, especially since today many boards either can't be cut & jumped or because our Clients can't afford the time and money for an extensive debug/bring-up process. In 2002, we decided to open up a specialized SI service bureau for "schematic-to-gerber" SI consulting as a result of the increasing demand for such services. That's Nuvation-SI, and you can reach us at si@nuvation.com.
Coming from a predominantly analog engineering background, I approach Signal Integrity as an analog/RF engineering task. SI analysis begins at the point where the digital signals are so fast (PRR of ≥100MHz and rise times <1ns) that they can no longer be treated as simple digital signals and the PC board as a simple interconnect medium. At these rates the signals become microwave signals and the board interconnects become transmission lines. Under these conditions, a trace length of a few inches presents a delay equal or greater than some of the active components and the time error represented by a few inches of trace can violate setup and hold times for many of the newer devices, an unterminated stub length of ½ inch becomes a source of ringing that can last for several ns. At low pulse rates, an extra delay of a 0.5ns, ringing, or a crosstalk component lasting 2 or three ns do not effect the proper functioning of the circuit. However, on a board with clock periods of < 10ns, a few ns of extraneous signals can seriously compromise the operation of the board.
The expertise and tools that my team and I bring to the problem is unique and it allows us to evaluate complex designs and the board layouts associated with them as part of the design rather than as a debug exercise. Our approach prevents unwanted signals, ground bounce, improper decoupling, and EMI caused by improper transmission line and ground return paths design. This is far preferable to fixing the problem in the hardware lab and helps avoid expensive and time-consuming re-spins.
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When should I consider SI analysis?
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If you're doing high-speed digital designs (100MHz +), analog/RF (50MHz +), with high component-densities and sub-nanosecond edge rates (high switching-speeds), I recommend you read on. Boards with banks of QDR, DDR, precision analog circuitry, low noise tolerances for GPS and wireless applications, high-speed interfaces like PCI-X, and multi-GHz chip-to-chip or board-to-board communication require SI analysis.
As boards get faster and smaller, a multitude of issues arise that require treatment. These issues include:
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High-Speed Digital (100MHz - 10GHz):
Overshoot/Undershoot, Impedance Matching, Signal Slope Requirements, EMI/EMC Analysis, Ringing, Bus Architecture, Bypass/Decoupling Capacitors, Board Delay & Timing, Trace Separation, Low-skew Clocking, Fast Switching, Cross-talk, Ground Bounce, Split Ground Planes, Shielding
Analog / RF (50 MHz - 40GHz):
Noise Figure, Substrate Noise, Active Component Parameters, Parasitic Coupling, Width/Spacing/Length of Fingers, Transmission Lines, Grounded Transmission Line, Discontinuities, RF Signal Control, Non-linear / Linear Noise of Non-linear Devices, Optimization Limits, Tuning to standard values, EMI/EMC Analysis
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SI Analysis makes sure that these issues are analyzed and minimized through specifying layout constraints, parts placement, PCB material and stack ups, trace lengths and so on.
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How do I get started with Nuvation-SI?
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Before we begin, we require the following inputs:
 Schematic / Netlist (with pre-named critical nets and PDF)
BOM
Data sheets of all components
IBIS Models for all applicable components
Listing of Net speeds
Setup/hold times for all applicable components
We prefer to begin with a design review involving your engineers, myself and my team, and your board schematic(s). As a standard practice, you are probably already doing peer reviews internally before sending any files out. Still, you'd be surprised at how many critical errors we catch. We have seats of OrCAD, ViewLogic, and Protel here and prefer to get both the source files and a searchable PDF. We want you to make any changes to the schematic for document control purposes. After ensuring a clean base design and that the net list will be structured properly, we load the net list together with the board outline and stack up into the SI tool(s) and proceed to perform a preliminary placement and analysis.
At this point we also load the IBIS and DML models. Sometimes we have to create custom IBIS models in SPICE or work with your component vendors to get or build IBIS or DML models. IBIS 3.0 does not support interconnects >1GHz so DML models are preferred. IBIS 4.0 also handles >1GHz. If you're not familiar with gathering and verifying IBIS models, we can do this and we have developed a fairly large library here as well. There is an extra charge for this so you may want to get in the practice of collecting them along with the datasheets needed for layout.
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What tool flows do you use, how, and when?
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Oftentimes we will use Cadence SPECCTRAQuest as the primary SI tool due to its range of capabilities and process integration with Cadence Allegro, our preferred layout tool. Occasionally there are circumstances that require Mentor (Innoveda) HyperLynx to Mentor Expedition (VeriBest); another tool flow we utilize here. One drawback of SPECCTAQuest is that it is less than ideal for multi-GHz circuits and does not simulate analog placements. (Another drawback is that it's a very convoluted tool, takes a long time to learn, and my boss says it's not inexpensive to own and maintain).
We typically use SPICE and/or Eagleware GENESYS tool flows for multi-GHz simulations and our own best practices for RF and low-noise/precision analog. With high-speed projects that involve many multi-GHz interconnects, I use PSPICE to model transmission line effects of the traces in the frequency domain. The response is then transformed back into the time domain to check the resulting pulse waveform. Besides driving the tool flows, the real key is in the interpretation and setup which is based on experience and understanding. This is where I earn my keep.
During the analysis we produce a set of design rules (constraints) for layout. These constraint files specify such things as trace impedance, maximum stub lengths, trace separation, crosstalk targets, maximum trace length, trace length matching requirements, etc. One benefit of using SI tools to produce the constraints is that the boards are not over-constrained, which otherwise leads to a long iteration cycle and some guesswork between you and your PCB layout service bureau. SPECCTRAQuest allows us to group placements in "rooms" which helps tremendously with layout. The constraints we generate ensure that the layout will function as an integral part of the design to ensure the proper performance of the board. We can also simulate various PCB materials and stack ups to optimize DFM and COGS.
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What about DFT?
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During the layout process we'll need to pay attention to DFT for JTAG Boundary Scan test coverage and ICT test points. There are a lot of points that you simply can't nail. We've taken a number of designs through DFT and have some techniques that yield amazingly high-test coverages (95% or better in many cases). In general, you don't want to nail anything over 1GHz or sensitive analog circuits for ICT. If you do, the pads needed to provide the test points add parasitic capacitance and/or stubs, which changes the functioning of the circuit.
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What do you recommend for PCB fab materials and vendors?
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Another sidebar here is that you can't use standard FR-4 reliably for many circuits operating over 1 GHz and expect them to work properly. FR-4 is not isotropic. FR-408/FR-406 is something we use frequently since it presents a reasonable compromise between performance and cost. Teflon or Epoxy-based materials, such as Rogers or Duroid, are designed specifically for high frequency analog or ultra-fast digital but are generally cost prohibitive for any but the most critical high frequency designs. You also need to confirm that your fab house can manufacture controlled impedance boards. If the fab house you plan on using does not know what "isotropic" means or they have never heard of a field solver program, I would suggest going elsewhere. I recommend that you ask your CM exactly how they measure impedance before cutting the PO. If your CM is contracting-out the PCB fab, you may want to interview their supplier as well. We can assist in this process if you like. So far we've found only a couple of shops in the US that can manufacture to the tolerances and consistency required for these designs. Ambitech is one of the best out there.
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Who should do layout?
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We typically outsource this task to a firm that specializes in layout. We tend to drive the layout process but will involve you at placement and routing design reviews and other points that may come up along the way. If you prefer to work with your own PCB layout service bureau and come back to us for post-route simulations that can be arranged too.
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What is Post-Layout SI?
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After the board has been placed and routed, the resulting board file is then imported back into SPECCTRAQuest for post-layout SI analysis. SI simulation is run on the layout using the final line lengths, widths and component placement. This last simulation emulates the performance of the board.
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Sometimes we have to modify the routing that we can do manually here. If there are some remaining issues that can't be dealt with here, then another constraints file is generated and the process is re-iterated, until all issues are cleared. If no faults remain, then the validated layout is ready for fabrication.
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What should I expect as a result of using Nuvation-SI?
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When the final product is compared to the final simulation, the real performance will match the simulation to better than 90%. Still far better than without SI, where it's common to have issues with over-constraining, iterative constraint changes and guesswork, and trial and error re-spins. A re-spin alone can cost six-figures+ for engineering time, wasted fabs/assemblies/parts, and lost revenues. Our process may add several weeks or more to a standard layout process but will greatly reduce risk to schedule, functionality, and budget.
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What if I only need some basic consultation?
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The process I've been describing is our recommended approach to complex designs. If you still feel that you only need a portion of these services, we have pared-down packages for such a la carte services as schematic design reviews, critical signal modeling and layout guidelines, layout reviews, and other consulting services.
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 Signal Integrity Brochure (PDF)
Nuvation-SI homepage
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