This issue, the device spotlight shines its light on the latest addition to the Xilinx Virtex family:  The Virtex™-5 FPGA.  Nuvation has always been highly focused on FPGA-based designs so when a new device family hits the streets we get really jazzed by the new features and applications.

Known to be the world's first 65nm FPGA family fabricated in 1.0V, triple-oxide process technology, the Virtex-5 is packed with 1200 I/O pins, low-power RocketIO™ serial transceivers, built-in PCI Express endpoint and Ethernet MAC blocks, along with other hardened IP.

Two platforms of the FPGA are available today, the LXT, optimized for high-performance logic with serial I/O, and the LX, optimized for high-performance logic.  Nuvation has already begun design starts with Virtex-5 LX, so for the purpose of this article we will be focusing our attention here.

Virtex-5 LX vs. Virtex-4

Performance

The key improvements in the Virtex-5 FPGA compared to the Virtex-4 family come from the ExpressFabric technology, on-chip memory, embedded DSP blocks, high-speed I/O interfaces, high-speed memory interfaces, new clock management, and Sparse Chevron Packaging technology. Table 2 shows a side-by-side comparison of system performance.

ExpressFabric Technology

New ExpressFabric technology delivers Real 6-LUT architecture to boost performance by 30%. New diagonally symmetric routing enables CLB connections through fewer switches for smaller routing delay.

On-chip Memory

Abundant internal Block RAM, running at up to 550 MHz, allows you to buffer data for efficient processing. You can also configure these memories as 550 MHz FIFOs without consuming extra resources.

Embedded DSP Blocks

The 25 x 18 multiplier in the DSP48E slices allow single-precision floating point calculation and implementation of wide filters for a variety of DSP functions, without consuming logic fabric resources. Dedicated routing supports efficient adder-chain architectures that overcome the performance bottlenecks of adder trees.

High-Speed I/O and Memory Interfaces

With 1.25 Gbps LVDS and 800 Mbps single-ended I/O supporting a wide range of electrical standards, Virtex-5 FPGAs offer the flexibility to achieve the highest possible bandwidth for chip-to-chip, board-to-board, and box-to-box connectivity.
SelectIO™ blocks, along with ChipSync™ circuitry, make it easier to implement high-speed source-synchronous memory interfaces.

Performance Enhancing Technologies

Virtex-5 FPGAs ensure clock and data signal integrity by incorporating a low-skew, low-jitter 550 MHz differential clock structure. New clock management tiles offer greatly expanded flexibility by combining digital clock managers (DCM) for precise clock synthesis and phase-locked loops (PLL) for reducing jitter.
Sparse Chevron Packaging technology and flip-chip assembly techniques, enabled by the proprietary ASMBL™ technology and abundant PWR/GND pins, improve signal integrity by minimizing package and PCB inductance. On-chip active signal termination technology provides digitally-controlled impedance (DCI) to optimally tune component interconnects while minimizing system component count and cost.
Sparse Chevron Packaging technology:

• Reduces inductive crosstalk by providing a low-impedance return path near every I/O pin
• Reduces the number of external decoupling capacitors, reduces board layer count, and simplifies board design by encapsulating low-inductance, on-substrate bypass capacitors
• Lowers inductance using continuous Power/GND planes.

Lower power consumption per MHz results in greater performance within your power budget. As Virtex-5 FPGAs has reduced dynamic power consumption with 65nm technology, they are also known to have minimized static power consumption with triple-oxide technology.


Conclusion

In addition to configuration with Xilinx Platform FLASH devices, Virtex-5 FPGAs offer new low-cost options, including SPI flash memory and Parallel flash memory.  Both LX and LXT platforms include enhanced bitstream management to simplify in-system reconfiguration and increase reliability.  Multi-bitstream management supports warm/cold boot of the FPGA as well as providing for a safe bitstream if FPGA errors occur. Background CRC checking capability is implemented. 

Software-based bitstream encryption and on-chip bitstream decryption logic uses dedicated memory to store the 256-bit encryption key, protecting the design with AES  (Advanced Encryption Standard) technology.  The user can generate the encryption key and encrypted bitstream using Xilinx software and during configuration, the device device decrypts the incoming bitstream.

Designed to replace ASICs and ASSPs in many applications, the Virtex-5 consumes less power, makes less noise, uses less space, and slashes overall parts costs while providing more processing and more performance.   For more information on simplifying and optimizing your hardware with Virtex-5 technology, please contact Nuvation at sales@nuvation.com, or through one of the following links:

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