Click Here!

Winter 2007 Frontpage | Subscribe | Feedback 


In This Issue

USB on Vista

DSP-based
IP Camera

Device Spotlight:
Xilinx Virtex-5


Previous Issues

ATCA: The NexGen Telecom Standard

Video Processing in FPGA vs. DSP

Signal Integrity 101
Series: P1 | P2 | P3

Device Spotlights

Pixim D2500
Gennum VXP

IPFlex DAPDNA-2
TI DaVinci

Lattice XP
TI DM642 DSP
ADI TigerSharc
Altera's Nios II
Airgo Wireless



Nuvation HEADLINES 

New Events

» 

Nuvation at TI Developer's Conference,
Dallas TX, Mar 7-9

»  Nuvation at ISC West, Las Vegas, Mar 28-30

New Affiliations

» Microchip
Authorized Design House
»  CYPRESS Partner
CYPros Certified USB Consultant
» TI Low-Power RF Developer Network Member
»  TI DaVinci DSP Partner Expansion
 


NUVATION SATA IP NEWS UPDATE!

As many of you know, Nuvation introduced its SATA Host Controller IP core for FPGA target devices in 2005. Our licensable SATA Host Controller is a drop-in IP block used to interface to external SATA devices. The core includes the transport and link layers of a host controller, also known as a Host Bus Adapter (HBA). The core supports an advanced firmware interface called Advanced Host Controller Interface (AHCI) from Intel.  AHCI simplifies the HBA down to a data-mover, while providing a clean mechanism for command queuing.  The core includes full documentation and support and has been independently certified by Altera. 

Nuvation is now releasing an updated version which will interoperate with external 1.5G and 3G PHYs from a major semiconductor firm (yes we are disclosing the PHY vendor but it requires an NDA).  Nuvation is providing turnkey support for the FPGA IP and PHY solution, in low or high-volume applications.

This solution is geared for any product that needs both an FPGA and one or more SATA storage devices.  Our SATA IP can be integrated with soft processors, video processing blocks, PCI/PCIe cores, USB, and/or custom IP blocks to create FPGA-based SoC solutions.  Each instantiation of our SATA Host Controller uses only 4,800 Altera LEs and less than 24k Memory Bits, or 2488 Slices & 7 BlockRAMs in a Xilinx target. 

Now, for the first time, SATA designs can be implemented with low-cost FPGAs such as Cyclone and Spartan-class devices.  High-density FPGA designs in Stratix or Virtex-class devices can be enabled without the cost premium of an integrated transceiver.  And when a design requires SATA plus additional serial protocols such as PCIe or GbE, the FPGA’s integrated transceiver can be used with the protocols that they are more commonly characterized for -- while utilizing a SATA-specific external PHY for the unique electrical attributes of SATA. 

An evaluation version of our SATA Host IP is available today, as are samples and production quantities of the PHYs (varies by part #).  We are also gathering requirements from customers who may be interested in SAS.

Please contact us for more information and licensing options, ip@nuvation.com. 


Additional Quicklinks:


Ask Nuvation a Technical Question
Get an Online Quote










Search Nuvation.com
Customer service
· To subscribe yourself or a friend, please click here.
· Questions? Comments? Send us your feedback.





Copyright © Nuvation Research Corporation 2007. All rights reserved.
Privacy Policy | About Nuvation | NUVATION.COM