ARM Cortex-M1 Processor on an Altera Device?
Platform Independence Evaluation

Faisal Ali
Design Engineer
Nuvation

ARM recently released a soft processor core called the Cortex-M1, capable of being implemented across Actel, Altera, and Xilinx FPGA devices.  As a leading design firm with deep experience in embedded processors, Nuvation decided to evaluate the new M1 for FPGAs.  We integrated the Cortex-M1 in different FPGA synthesis tool flows, and evaluated software development support, software libraries and most importantly, the cores’ performance. Here’s what we found:

1. Why use an ARM Cortex Processor?

The main benefit of Cortex-M1 is that it is platform independent. By contrast, other soft processors used today in FPGA-based designs are provided by the FPGA vendors and they can only be targeted to their own FPGA devices. Altera’s NIOS-II can only be used in Altera’s FPGAs, and Xilinx’s MicroBlaze can only be used in Xilinx FPGAs. However, the ARM Cortex-M1 processor works across most leading FPGA devices, with the notable exception of Lattice. All optimizations for any particular FPGA device in the Cortex-M1 core have been carried out within a single RTL source. This means designers can easily perform migration from one FPGA device to another with minimal effort. Currently, the Cortex-M1 can be targeted to the following FPGA device families:

The Cortex-M1 core is available free of charge if the design is targeted for Actel FPGAs.  Xilinx and Altera targets are licensed by ARM for a nominal fee. 

The other main benefit of using the Cortex-M1 processor is the availability of extensive software support. The software written for Cortex-M1 is upward compatible with other members of the Cortex family.

2. Main Features of Cortex Processor

The 32-bit Cortex-M1 core microprocessor has the following key features:

• Three-stage pipeline
• Three-cycle hardware multiplier
• Thumb-2 instruction set
• Tightly Coupled Memories (TCMs): The Tightly Coupled Memories are low-latency memories internal to the component. There is a separate Instruction Tightly Coupled Memory (ITCM) for instruction accesses and Data Tightly Coupled Memory for data accesses. Each of these has a configurable size from 0KB to 64KB. Highest performance is achieved when code is executing from the TCMs. It should be noted that these TCMs are not part of the original Cortex-M1 core. Interfaces to these TCMs are available in the original Cortex-M1 core and these would be either added or removed from the finally synthesized Cortex-M1 component depending upon the user selection.
• 13 general-purpose 32-bit registers plus link register, program counter, program status register and two banked stack pointers.
• Integrated Nested Vectored Interrupt Controller: The core contains a tightly-coupled Nested Vectored Interrupt Controller (NVIC) supporting up to 8 interrupts with 4 levels of priority.
• Removable debug support: Cortex-M1 core is available for instantiations in two versions; one with debug support and the other without the debug support.
• Bus Interface:For external memory accesses, the original Cortex-M1 core uses AMBA 3 AHB-Lite Bus protocol. For implementation on Altera FPGAs using Altera SOPC builder tool the AHB-Lite Bus is replaced (could be wrapper) with Altera Avalon Bus interface. (Currently, this is ‘unknown’ to us which bus interface is used by Cortex-M1 for implementation on Xilinx FPGAs. By following the Altera example, it seems the Bus interface used in Xilinx devices would be either OPB or PLB).

3. Configurable Parameters

The Cortex-M1 core allows the user to configure the following parameters:

4. Operating System Support

The following operating systems support Cortex-M1:

• Express Logic Thread X RTOS
• Micrium uC/OS-II RTOS
• Mentor Nucleus RTOS

It should be noted that the Cortex-M1 core doesn’t contain a Memory Management Unit (MMU).  Operating systems that require MMU, such as Embedded Linux, cannot run on Cortex-M1.  This is a significant advantage for Xilinx’ new MicroBlaze v7 with MMU for applications which require this level of functionality. 

5. Plug & Play Synthesis Flow on Altera FPGAs

Using the Altera tool flow, the Cortex-M1 core is available as a component in Altera’s SOPC builder and can be instantiated either with a debug support or without the debug support. For implementation in Altera FPGAs, the Avalon interface allows easy connections between the Cortex-M1 and other peripherals. The configurable parameters are the same as outlined in section 3.  We chose the Altera Cyclone III device as the target FPGA for our evaluation.

The synthesis flow was similar to the flow used for NIOS implementation. First a system consisting of Cortex-M1 processor and its peripherals is generated using SOPC builder. After successful system generation, the entire system is instantiated in a top level Verilog/VHDL file in Quartus project followed by a synthesis of the whole design. 

The synthesis was successful without any notable issue. The total size of ITCM and DTCM should not exceed 48 KB in a Cyclone III device.

6. Performance Evaluation

For the performance evaluation, a reference design provided with the Cortex-M1 FPGA development kit was used. The reference design contained very basic components that are present in almost all embedded systems:

• Cortex M1 processor core synthesized with  ITCM (Instruction Tightly Coupled Memory), DTCM (Data Tightly Coupled Memory), NVIC (Nested Vectored Interrupt Controller) and internal system timer.
• System Interconnect Fabric (Avalon)
• Interval Timer
• Parallel I/O for user inputs.
• Parallel I/O for LEDs
• JTAG UART
• Tristate Bridge for external memories
• System ID Peripheral;
• External SSRAM PLL
• External SRAM Controller
• External Flash Memory Controller

Altera Quartus II 7.1 with SP1 was used for synthesis. To compare its performance with Altera soft processors, the same reference design was used with a NIOS II/f processor. NIOS II/f is the largest processor in the Altera NIOS family, with instruction cache, data cache, hardware multiply, hardware divide, barrel shifter and dynamic branch prediction units. The NIOS II/f processor was synthesized with three different configurations. The results are summarized in the following table:

7. Software Development Environment

µVision IDE provided by Keil Development Tools was used to develop software for the Cortex-M1 core (also supports other ARM processors). It uses ARM’s Realview Compiler to generate optimized machine code for the corresponding ARM’s processor.

i. Features

The µVision IDE provides the following features for embedded software development:

• Full-featured source code editor
• Device database for configuring the development tool setting
• Project manager for creating and maintaining your projects
• Integrated make facility for assembling, compiling, and linking your embedded  applications
• Dialogs for all development tool settings
• True integrated source-level Debugger with high-speed CPU and peripheral simulator
• Advanced GDI interface for software debugging in the target hardware and for connection to Keil ULINK
• Code coverage to provide statistical analysis of the program execution.
• Flash programming utility for downloading the application program into Flash ROM
• Links to development tools manuals, device datasheets & user’s guides.
  

The software development flow for Cortex-M1 in µVision IDE consisted of the following steps:    

1. Start a new project in µVision IDE.
2. Select the Cortex-M1 processor as the target processor.
3. Select the Realview Compiler.
4. Write programs in C or Assembly.
5. Write the startup code.
6. Compile the program and fix the errors.
7. Select the desired Flash Memory.
8. Program the Flash Memory.
9. Run the program.

The evaluation version of the Realview kit was used to measure the performance of the Cortex-M1, which had the following limitations:

• Image ROM size of the generated application is limited to 16KB maximum.
• The linker does not accept scatter-loading description files for sophisticated memory layouts.
• The base address for code/constants is restricted to 0xXX000000, 0xXX800000, or 0x00080000 whereby XX stands for 00, 01, ..., FF. This allows memory start address like 0x00000000, 0x12800000 and so on.
• It is not possible to generate position independent code or data.
• The compiler does not generate a listing file.
• The Evaluation Version cannot be used to create commercial products.

8. Conclusion

The synthesis flow of the Cortex-M1 core in Altera Quartus and its software development in µVision IDE was evaluated with positive results. The synthesis and software development process was quite smooth and did not pose any problems to the designer. Cortex-M1 could be a good choice in FPGA-based designs if the design is intended to be ported to multiple FPGA platforms in the future. However, performance results for Cyclone III FPGA have showed that Altera NIOS II/f processor offers better performance. So if the design is only intended to be implemented in Altera devices, NIOS is a better choice. Likewise with Xilinx and its MicroBlaze processor. In addition, the designers should also consider the costs involving the use of the Cortex-M1 processor before making their final decision. Keep in mind that two licenses are required; one for Cortex-M1 core (except with Actel devices), and the other for µVision IDE for software development.

For more information please contact Nuvation at sales@nuvation.com.

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