Nuvation

Nuvation has assembled the most advanced signal integrity tool libraries available, driven and interpreted by seasoned professionals with decades of high-speed design and RF modeling experience. According to our clients and partners, Nuvation has achieved an unparalleled “first-time-right” track record with high-complexity PCB designs.

Nuvation-SI is a service bureau within Nuvation for clients who develop designs in-house and need specialized support and simulations for high-speed and high-density PCB design. Nuvation-SI offers two packages for OEMs who have completed their schematic design.

• SI Consulting Packaging includes:
  • Pre-layout simulations (bus ringing, bounce, xtalk, impedance, and timing)
  • PCB materials, stackup, placement, and routing guidelines
  • Post-layout simulations

• SI Turnkey Packaging includes:
  • System Architecture and Schematic design review
  • IBIS, HPSICE, and DML model collection, verification, and creation as required
  • Consulting with client’s PCB Fab, Assembly, and Test vendors, introduction to alternates if needed
  • Pre-layout simulations
  • PCB layout (includes layout placement & routing reviews with client)
  • ICT fixtures & code as required
  • JTAG Boundary Scan Test Vector Generation as required
  • Post-layout simulations
  • Final gerbers, silk screens, valor checks)

Project Examples

Military Flight Simulator · 3 very advanced boards and backplane through our turnkey service · Board, backplane, and system-level simulations · Included extensive analog architecture design support · Over 90% ICT coverage achieved · Averted expensive Nelco or GTek, designed to FR-406/408 at 10% premium over standard FR-4		FibreChannel Host Bus Adapter · Signal & Power Integrity analysis · Analyzed Fiber-Channel Host Bus Adapter, SRAM & DDR DRAM interfaces · DDR DRAM; 125MHz clock, 250MHz 32-bit data +7-bit ECC · SRAM; 125MHz clock, 32-bit data + 4-bit parity
10G Telecom Board · SI consulting project for 10GHz circuit design and simulations. · Included placement, routing, stackup, and fab material guidelines. · Pre- and Post-Layout simulations		Timing Analysis · Network Search Engine (NSE) Evaluation Board · Signal Integrity timing delay report · Trace and package I/O delaysand maximum signal speed calculation · Analyzed cascade signals between NSE devices including command/result buses between interface FPGA · 133MHz clock, 266MHz data rate, HSTL type @ 1.5V