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ATA-5 PLB for Xilinx


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	“Nuvation has been a select member of our Certified Design Center program for several years, as well as a design services vendor to Altera. We have been consistently impressed with the caliber of their organization, the time-to-market acceleration that they enable, and their strong track record across our broad customer base.” -- Altera


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ATA-5 Host Controller with PLB interface for Xilinx Devices

Features | Target Device | Command Set | Block Diagram | Contact |

Description
The ATA-5 / UDMA-66 IDE Core is a drop-in ATA-Host IP core used for interfacing to an ATA-device. It handles all transactions on the IDE bus for various commands that are dispatched from the system. After a command is dispatched, the ATA-core executes the command on the ATA device. Once the command execution is completed, the final status is reported to the system side. At that time, the system can execute a new command.

The ATA-5 core features a PLB interface for use in all Xilinx FPGA devices. Nuvation’s ATA-5 controller also connects directly to the Local Link DMA ports of the PPC440 specifically for Virtex-5 FXT devices. In devices other than Virtex-5 FXT, the core should be used with the Xilinx XPS_LL_FIFO component to connect the ATA-5 local Link interface to PLB.

Applications often include controllers for HDDs, Compact Flash, and Solid State Disk Drives. Utilizing available FPGA resources can reduce PCB real estate and product cost. Multiple instantiations of the ATA core can be implemented for RAID-type architectures.

The ATA-5 core from Nuvation is available under IP core license agreements. Licensee Deliverables include the Netlist, Verilog Test Bench, Detailed User Guide, Support, and Warranty. Extended Support, Extended Warranty, and Source Code licenses are also available.

Features

ATA-5 standard compliant host
UDMA-66 transfer speed capabilities (66 MB/s max transfer speed)
RX and TX FIFOs for data transfer through the Core
DMA/UDMA and PIO data transfers supported
Dedicated signal for polling ATA-device status
Dedicated signal for executing Software Reset command
Two Clock domains: Core Clock and System Clock domains
PLB interface for command and status
LocalLink DMA interface for writing data to the ATA device
LocalLink DMA interface for reading data from the ATA device
Required Core Clock Speed: 100MHz
Available PIO Modes: 0 and 4
Number of ATA devices supported on the IDE Bus: 1
Optional LBA-48 support (module included upon request)

Target Device Family: Xilinx Spartan 3, Virtex II/Pro with PLB

Number of Slices: 911
Number of Memory Bits: 8,192

Target Device Family: Xilinx Virtex-5 with PLB and LocalLink

Number of Slices: 911
Number of Memory Bits: 8,192

Command Set

Check Power Mode
Identify Device
Idle
Idle Immediate
Initialize Device Parameters
Read Verify Sector(s)
Seek
Set Features
Set Multiple Mode
Sleep
Standby
Standby Immediate
Execute Device Diagnostic
Read DMA
Read Multiple
Read Sector(s)
Write DMA
Write Multiple
Write Sector(s)

Block Diagram

Nuvation ATA-5 Host Controller IP Core, PLB for Xilinx version

Contact
For more information please fill out the IP inquiry form or contact us by email at ip@nuvation.com.

Please download the product brief.