NUVATION | ATA-5 Avalon (SOPC) Core

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ATA-5 Avalon (SOPC) Core


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ATA-5 Core for Altera SOPC Builder

Features | Target Device | Block Diagram | Contact |

Description

The ATA-5 / UDMA-66 IDE Avalon Core is a drop-in ATA-Host IP core used for interfacing to an ATA-device. The core has all connections to interface to an Avalon bus and IDE bus. Two Avalon buses are used in the design. One bus controls writing to and reading from the taskfile registers needed for the data transactions. The second Avalon bus reads and writes the data to the ATA hard drive when a transaction is initiated. It handles all transactions on the IDE bus for various commands that are dispatched from the system.

The ATA-5 Avalon core from Nuvation is available either as an encrypted Netlist or as a source code license. This core is also available in Altera SOPC Builder for seamless integration into any design.

Features

ATA/ATAPI-5 standard compliant host
UDMA-66 transfer speed capabilities (66 MB/s max transfer speed)
RX and TX FIFOs for data transfer through the Core
DMA/UDMA and PIO data transfers supported
Dedicated signal for polling ATA-device status
Dedicated signal for executing Software Reset command
Two Clock domains: Core Clock and System Clock domains
Dedicated system side input bus for writing data to the ATA device
Dedicated system side output bus for data read from the ATA device
Required Code Clock Speed: 100MHz
Available PIO Modes: 0 and 4
Number of ATA devices supported on the IDE Bus: 1

Target Device

Altera Cyclone
Number of LE's: 1056
Number of Memory Bits: 8192

Block Diagram

Contact

For more information please fill out the IP inquiry form or contact us by email at ip@nuvation.com.

Please download the product brief.