Serial ATA Host Controller IP Core for Altera Devices
Features | Target Device | Block Diagram | 
Description
The Nuvation SATA Host Controller IP Core is a drop-in core used to interface between memory or memory mapped I/O and SATA devices. The core includes the transport and link layers of a host controller, or host bus adapter (HBA) and is fully compliant the SATA 2.6 specification at 1.5Gbps or 3Gbps. The core is compliant with the Serial ATA Advanced Host Controller Interface (AHCI) v1.3 specification. AHCI is a native Serial ATA interface that simplifies the HBA down to a data-mover, while providing a clean mechanism for command queuing. The Nuvation SATA core features an Avalon interface for easy integration in SOPC Builder environments.
Nuvation’s SATA Host Controller IO core is used frequently in applications that require an FPGA and also require r/w to SATA storage devices. Implementing SATA in spare FPGA resources can reduce PCB real estate and product cost. Medical Devices, Defense, Aerospace, Video Security, Scientific Instrumentation, and other markets are common users of Nuvation storage IP cores. Nuvation’s SATA Host Controller IP core can be implemented with multiple instantiations for RAID-type applications. It can also be implemented in conjunction with external Port Multiplier devices.
The SATA Host Controller AHCI/Avalon requires an integrated Altera SERDES which supports SATA electrical requirements. Currently, Stratix® IV GX is available with such SERDES support. Arria® II GX is planned, pending characterization tests. When implemented in Altera Stratix® IV GX, migration to Altera HardCopy® IV ASIC is available.
The SATA IP core is available under Nuvation’s Core License Agreement (CLA). Licensee deliverables include encrypted Verilog source, Verilog Test Benches, NIOS II test software, detailed user guide (with screen shots, etc), email technical support, and a one year warranty. Unencrypted source code licenses, extended support, extended warranty programs, and design customization services are also available from Nuvation. ITAR, CGP, 510k, and other regulatory requirements can be supported. Altera has distinguished Nuvation as a premier Certified Design Center.
This Product Brief is for BETA RELEASE customers. General Availability (GA) is pending final design verification testing in licensee products. Please contact Nuvation for more information, ip@nuvation.com.
Features
- Compliant to the Serial ATA AHCI 1.3 specification
- 32 command slots per port, and 1 port per HBA
- Supports both DMA and PIO protocols
- 3 clock domains: system, link/transport layer, and receive
- Out Of Band (OOB) signaling supported by Altera transceiver.
- Spread-spectrum clocking (SSC) supported by Altera transceiver.
- Avalon bus interface, integrated into SOPC Builder
- 32-bit internal buses in link and transport layers
- CONT primitive and “junk-data” scrambler to reduce EMI
- FIFOs between each architecture layer
- Shallow link-phy FIFOs for phase/frequency variations in external PHY
- Shallow transport-link FIFOs for flow control and temporary storage
- Deep DMA controller FIFOs for data-rate matching
- Supports native command queuing
- Supports command-list override
- Supports PIO multiple DRQ Block
- Supports auto-speed negotiation
- Support for FIS Switching, Async Notification, HotPlug, and other optional extensions to the SATA 2.6 specification available through customization services
- Number of Combinatorial ALUTs: 4,000
- Number of Memory ALUTs: 200
- Number of Registers: 3,500
- Number of Block Memory Bits: 38,912 (6 M9Ks)
Nuvation SATA Host Controller IP Core Architecture for Altera Stratix IVGX
FPGA SoC Implementation Example
Nuvation has been a select member of our Certified Design Center program for several years, as well as a design services vendor to Altera. We have been consistently impressed with the caliber of their organization, the time-to-market acceleration that they enable, and their strong track record across our broad customer base. 
