An Easier Verification Method for FPGA Designs

By Steve Miller | Sep 27, 2013

Recently, Senior Design Engineer Steve Miller was working on an FPGA design project that required taking multiple video inputs and processing them in real-time through an FPGA. Some of the necessary computations involved comparing images in two parallel video streams. Steve wanted to independently verify the FPGAs blocks prior to integration into the final product, but typical FPGA design verification methods using test cases (written in tools such as Aldec) would require writing tedious video stream test inputs and expected outputs for each test case.

In addition, the client wanted a simulation of the entire system to an accuracy that reflected the FPGA output to the least significant bit. Traditional image processing through tools like Matlab process the pixel data in floating point variables and could not guarantee this precision. In addition, the impact of rounding in truncation within the FPGA and special edge condition processing needed to modeled.

To solve both of these requirements, Steve developed a simulation tool called the Computational Model (CM). Written in C++, it allows the user to write equivalent block  objects in software and wrap a generic multi-input/output block interface around them. The simulation is platform-independent and can be compiled and executed in either Windows or Linux OSs.  The simulation collects groups of blocks (based on a configuration input) and executes them on one or more separate threads on the host computer.

The Computational Model

The CM can accept any arbitrary PNG image as an input and automatically provide the configuration of the input image to all connected blocks. The output of the CM provides both the configuration of the block and the resulting input and expected output data streams. This meant that a boilerplate test case could be developed for the verification of the FPGAs. A tester simply had to apply the same block configuration to his test case and make sure that the output matched the expected output. Several test case scenarios could be run from the same test case by providing different CM simulation runs of different test images. The CM could automatically execute images of a couple lines or full 4k images without extra configuration changes between runs.

The simulation allowed multiple threads of groups of blocks to be defined and executed. Using core processing functionality, Steve was able to create a simulation that took one or several  of the block functions in the FPGA and provided an expected output based on the applied input. Then the results for any image could be verified against the FPGA and the simulation, and Nuvation Engineering could deliver a known-good product to a satisfied client.

Check out the video below to learn more about the Computational Method.

Nuvation Engineering specializes in product development for the video industry, including complex video processing, image sensor interfacing and image processing, and 4K/high definition video designs. Contact Nuvation Engineering to learn about how our experienced engineering teams can get your product to market faster.