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Video Processing in an FPGA vs. DSP
Why some DSP algorithms will run better in an FPGA
What can an FPGA do for real-time video processing compared to a DSP device? With the low-cost FPGA market introducing new chips with higher density and performance, digital signal processing does not necessitate a pure off-the-shelf DSP device approach, especially in video applications. For example, video compression and decompression is at the core of numerous technologies including digital television, set-top boxes, digital satellites, HDTV, DVD players, video conferencing, web-based video, and digital cameras.
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System level processing rates for real-time video processing are soaring, placing critical demands on overall system performance. With these high demands, DSP-based video designs often use multiple DSP devices to provide the required throughput. However, implementing the same design with the parallel processing capability of an FPGA device meets performance requirements within a single device. To get an idea, the increase in speed of an average DSP algorithm running on a low-cost FPGA vs. a low-cost DSP can be roughly 1 order of magnitude, or up to 10 times faster in the FPGA.
Because FPGAs are essentially custom programmable hardware, the designer is able to trade off area against speed to meet requirements. For example, an FPGA may only need to run at 25MHz to perform four parallel computations for a signal processing function, whereas the same function in a DSP may require clock speeds of up to 1 GHz.
Even high-end DSP and microprocessors offer limited parallelism, memory flexibility, and interface capability. The integration of dozens of processors in a real-time design is non-trivial and provides serious complications including design complexity, form factor, power consumption, development time and cost. At the same time, standards of video quality are increasing, and the development of improved video compression algorithms is progressing. The use of FPGAs encompasses the high-end DSP architecture into one flexible device that can be updated seamlessly.
DSP device-based designs have traditionally included FPGAs on board for glue logic and processor peripherals. Now, primary DSP functionality can also be handled by the FPGA, including the glue logic, in one device. The results are reduced size, system complexity, and cost.
Besides replacing banks of DSPs, FPGAs are also an ideal candidate to offload computationally intensive processing from common low-cost microprocessor and DSP device-based designs. For product line extensions, which often increase throughput (primarily by increasing computation-heavy functions), FPGAs are used to extend the product life by taking on the extra computation.
The re-programmability of an FPGA is vital for distinguishing a video product in its market. Compression standards like MPEG4 and MPEG2 are based on the discrete cosine transform (DCT), which removes redundant pixel information that is unnoticeable to the viewer. The inverse discrete cosine transform (IDCT) is used to decompress the data. The DCT/IDCT algorithms are standardized and can be efficiently implemented in FPGAs. However, there are other components in MPEG encoding that are left undefined and provide the differentiation between products. These proprietary algorithms (for example: motion estimation and compensation) are constantly evolving. FPGA implementation can allow for the updating of these algorithms, and enhance product differentiation.
From a development perspective, high-performance DSP algorithms can be implemented on FPGAs with less risk than ASIC due to re-programmability. Dedicated hardware for DSP functionality can be achieved without the cost, schedule, and risk of developing an ASIC. The development tools for DSP implementation in FPGAs are highly evolved, catered for both FPGA and DSP engineers alike.
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Tool Flow
For Xilinx FPGAs, DSP modeling can be done with The MathWorks MATLAB® and Simulink™. Xilinx's System Generator for DSP through Simulink, converts these models to HDL. Users can also bring in their own HDL Modules via HDL co-simulation, or write MATLAB code for combinational control logic or statemachine. From this point onwards, standard FPGA tools can be used for synthesis including Xilinx XST, Synplicity's Synplify Pro, or Mentor Graphics' FPGAAdvantage. VHDL testbench and data vectors can be created by System Generator for DSP. These vectors represent the inputs and expected outputs seen in the Simulink simulation, and allow the designer to easily see any discrepancies between the Simulink and VHDL simulation results. FPGA Advantage can be used to conduct simulations of DSP systems prior to implementation. If doing HDL co-simulation, ModelSim is required.
For Altera FPGAs, DSP modeling is also done with The MathWorks MATLAB® and Simulink™. Altera's DSP Builder automatically generates HDL code from the models. Using the DSP Builder, designers can generate a register transfer level (RTL) design and RTL testbench from Simulink automatically. These files are pre-verified RTL output files optimized for use in Altera's Quartus II software for quick timing and simulation comparisons. The design flow also enables floating-point to fixed-point analysis. For HDL synthesis, Altera's Quartus II or Synplicity's Synplify Pro can be used.
Altera also offers a C-based design flow through the embedded processors and software tools such as SOPC Builder and DSP Builder. The DSP Builder tool is tightly integrated with SOPC Builder tool, providing a standard software design process to allow DSP designers to code their systems in C-code or assembly language. The SOPC Builder interface allows the user to build systems that incorporate Simulink designs and Altera embedded processors and IP cores.
AccelChip's DSP Synthesis is an alternative tool that takes DSP algorithms written as MATLAB M-files and generates synthesizable RTL and testbenches for implementation in FPGAs for both Xilinx and Altera FPGAs.
For the DSP engineer starting to work with FPGAs, the algorithm development is still done in MATLAB, and appropriate tools can be used to convert to RTL code. So, the need to learn Verilog or VHDL is not necessary. Learning to work with the rest of the tools in the flow will be beneficial and can be done with short tutorials or courses. FPGA engineers have an option to write the algorithms directly in HDL skipping the MATLAB models conversion step entirely. Licensable IP cores for real-time video processing algorithms are abundant.
For more information or help with DSP implementation in FPGAs for your video processing application, please contact us for a free consultation with our FPGA and DSP engineering experts.
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